Inventor · disambiguated record
Sarma Vrudhula
Also filed as: VRUDHULA SARMA
22 granted patents·4 pending applications·204 citations·filing 2006–2025
95Inventor score
Files withVRUDHULA SARMA12UNIV ARIZONA STATE3ARIZONA BOARD OF REGENTS FOR AND ON BEHALF OF ARIZONA STATE UNIV2GOWDA TEJASWI2UNIV ARIZONA2
Top patents by PatentIndex Score
26 records- 0194US9934463B2Neuromorphic computational system(s) using resistive synaptic devicesSEO JAE SUN·Filed 2016·Granted Apr 3, 2018·25 cites·11 claims
- 0294US9466362B2Resistive cross-point architecture for robust data representation with arbitrary precisionYU SHIMENG·Filed 2015·Granted Oct 11, 2016·35 cites·17 claims
- 0391US9876503B2Method of obfuscating digital logic circuits using threshold voltageVRUDHULA SARMA·Filed 2016·Granted Jan 23, 2018·16 cites·19 claims
- 0490US11356100B2FPGA with reconfigurable threshold logic gates for improved performance, power, and areaVRUDHULA SARMA·Filed 2020·Granted Jun 7, 2022·6 cites·15 claims
- 0588US8832614B2Technology mapping for threshold and logic gate hybrid circuitsVRUDHULA SARMA·Filed 2013·Granted Sep 9, 2014·13 cites·8 claims
- 0687US10447249B2Hold violation free scan chain and scanning mechanism for testing of synchronous digital VLSI circuitsVRUDHULA SARMA·Filed 2016·Granted Oct 15, 2019·4 cites·18 claims
- 0787US9473139B2Threshold logic element with stabilizing feedbackVRUDHULA SARMA·Filed 2015·Granted Oct 18, 2016·7 cites·18 claims
- 0887US9356598B2Threshold logic gates with resistive networksVRUDHULA SARMA·Filed 2015·Granted May 31, 2016·8 cites·20 claims
- 0986US9490815B2Robust, low power, reconfigurable threshold logic arrayUNIV ARIZONA STATE·Filed 2014·Granted Nov 8, 2016·7 cites·29 claims
- 1084US8601417B2Decomposition based approach for the synthesis of threshold logic circuitsGOWDA TEJASWI·Filed 2011·Granted Dec 3, 2013·14 cites·11 claims
- 1183US10551869B2Clock skewing strategy to reduce dynamic power and eliminate hold-time violations in synchronous digital VLSI designsVRUDHULA SARMA·Filed 2017·Granted Feb 4, 2020·5 cites·17 claims
- 1282US9306151B2Threshold gate and threshold logic arrayUNIV ARIZONA·Filed 2013·Granted Apr 5, 2016·6 cites·27 claims
- 1381US10250236B2Energy efficient, robust differential mode d-flip-flopVRUDHULA SARMA·Filed 2016·Granted Apr 2, 2019·5 cites·19 claims
- 1481US7630852B1Method of evaluating integrated circuit system performance using orthogonal polynomialsUNIV ARIZONA·Filed 2006·Granted Dec 8, 2009·13 cites·18 claims
- 1580US8164359B2Threshold logic element having low leakage power and high performanceLESHNER SAMUEL·Filed 2009·Granted Apr 24, 2012·13 cites·23 claims
- 1679US9933825B2Determining parameters that affect processor energy efficiencyARIZONA BOARD OF REGENTS FOR AND ON BEHALF OF ARIZONA STATE UNIV·Filed 2014·Granted Apr 3, 2018·6 cites·16 claims
- 1777US8181133B2Combinational equivalence checking for threshold logic circuitsGOWDA TEJASWI·Filed 2009·Granted May 15, 2012·12 cites·35 claims
- 1871US10795809B2Non-volatile logic device for energy-efficient logic state restorationYANG JINGHUA·Filed 2019·Granted Oct 6, 2020·3 cites·18 claims
- 1966US10133323B2Processor control systemARIZONA BOARD OF REGENTS FOR AND ON BEHALF OF ARIZONA STATE UNIV·Filed 2014·Granted Nov 20, 2018·5 cites·23 claims
- 2066US2023385624A1Computing in memory with artificial neuronsVRUDHULA SARMA·Filed 2023·Application pending·0 cites
- 2165US2024419955A1System and method for in-memory image processingVRUDHULA SARMA·Filed 2024·Application pending·0 cites
- 2263US12327075B2System and method for clock distribution in a digital circuitVRUDHULA SARMA·Filed 2024·Granted Jun 10, 2025·0 cites·19 claims
- 2357US2025322226A1Quantized neural network circuitVRUDHULA SARMA·Filed 2025·Application pending·0 cites
- 2452US11599779B2Neural network circuitry having approximate multiplier unitsAzari Elham·Filed 2019·Granted Mar 7, 2023·1 cites·18 claims
- 2550US2022121915A1Configurable bnn asic using a network of programmable threshold logic standard cellsUNIV ARIZONA STATE·Filed 2021·Application pending·0 cites
- 2645US12057831B2Threshold logic gates using flash transistorsUNIV ARIZONA STATE·Filed 2020·Granted Aug 6, 2024·0 cites·11 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →