Inventor · disambiguated record
Sebastien Hily
Also filed as: HILY SEBASTIEN
19 granted patents·3 pending applications·106 citations·filing 1999–2024
93Inventor score
Technology areasG06F
Top patents by PatentIndex Score
22 records- 0183US11847012B2Method and apparatus to provide an improved fail-safe system for critical and non-critical workloads of a computer-assisted or autonomous driving vehicleINTEL CORP·Filed 2020·Granted Dec 19, 2023·2 cites·24 claims
- 0277US7603527B2Resolving false dependencies of speculative load instructionsINTEL CORP·Filed 2006·Granted Oct 13, 2009·8 cites·30 claims
- 0371US7590784B2Detecting and resolving locks in a memory unitINTEL CORP·Filed 2006·Granted Sep 15, 2009·6 cites·12 claims
- 0470US7418552B2Memory disambiguation for large instruction windowsINTEL CORP·Filed 2003·Granted Aug 26, 2008·13 cites·30 claims
- 0569US12385975B1Integrated circuits including error protection of fields in transferred information and field-based error signals and related methodsAMPERE COMPUTING LLC·Filed 2024·Granted Aug 12, 2025·0 cites·31 claims
- 0669US6591342B1Memory disambiguation for large instruction windowsINTEL CORP·Filed 1999·Granted Jul 8, 2003·44 cites·24 claims
- 0768US9081688B2Obtaining data for redundant multithreading (RMT) executionHINTON GLENN J·Filed 2008·Granted Jul 14, 2015·4 cites·15 claims
- 0865US7516313B2Predicting contention in a processorINTEL CORP·Filed 2004·Granted Apr 7, 2009·10 cites·31 claims
- 0961US8793689B2Redundant multithreading processorHINTON GLENN J·Filed 2010·Granted Jul 29, 2014·1 cites·23 claims
- 1061US7174428B2Method and system for transforming memory location references in instructionsINTEL CORP·Filed 2003·Granted Feb 6, 2007·8 cites·29 claims
- 1160US9594648B2Controlling non-redundant execution in a redundant multithreading (RMT) processorHINTON GLENN J·Filed 2008·Granted Mar 14, 2017·2 cites·12 claims
- 1257US11966750B2System-on-chip management controllerAMPERE COMPUTING LLC·Filed 2022·Granted Apr 23, 2024·0 cites·20 claims
- 1355US9405545B2Method and apparatus for cutting senior store latency using store prefetchingSHWARTSMAN STANISLAV·Filed 2011·Granted Aug 2, 2016·1 cites·22 claims
- 1453US7752423B2Avoiding execution of instructions in a second processor by committing results obtained from speculative execution of the instructions in a first processorINTEL CORP·Filed 2001·Granted Jul 6, 2010·3 cites·32 claims
- 1552US7130965B2Apparatus and method for store address for store address prefetch and line lockingINTEL CORP·Filed 2003·Granted Oct 31, 2006·3 cites·37 claims
- 1650US7640419B2Method for and a trailing store buffer for use in memory renamingINTEL CORP·Filed 2003·Granted Dec 29, 2009·1 cites·27 claims
- 1749US7457932B2Load mechanismINTEL CORP·Filed 2005·Granted Nov 25, 2008·0 cites·25 claims
- 1848US12182417B2Address-range memory mirroring in a computer system, and related methodsAMPERE COMPUTING LLC·Filed 2022·Granted Dec 31, 2024·0 cites·19 claims
- 1944US7475225B2Method and apparatus for microarchitecture partitioning of execution clustersINTEL CORP·Filed 2005·Granted Jan 6, 2009·0 cites·12 claims
- 2044US2008059753A1Scheduling operations corresponding to store instructionsHILY SEBASTIEN·Filed 2006·Application pending·0 cites
- 2143US2007130448A1Stack trackerINTEL CORP·Filed 2005·Application pending·0 cites
- 2238US2008072019A1Technique to clear bogus instructions from a processor pipelineSODANI AVINASH·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →