Inventor · disambiguated record
Sean James Salisbury
Also filed as: SALISBURY SEAN · SALISBURY SEAN JAMES
27 granted patents·9 pending applications·38 citations·filing 2007–2024
93Inventor score
Top patents by PatentIndex Score
36 records- 0190US10942878B1Chunking for burst read transactionsADVANCED RISC MACH LTD·Filed 2020·Granted Mar 9, 2021·5 cites·20 claims
- 0288US9507716B2Coherency checking of invalidate transactions caused by snoop filter eviction in an integrated circuitADVANCED RISC MACH LTD·Filed 2015·Granted Nov 29, 2016·8 cites·22 claims
- 0387US12174738B2Circuitry and methodADVANCED RISC MACH LTD·Filed 2022·Granted Dec 24, 2024·1 cites·20 claims
- 0487US9727466B2Interconnect and method of managing a snoop filter for an interconnectADVANCED RISC MACH LTD·Filed 2015·Granted Aug 8, 2017·6 cites·19 claims
- 0581US10565146B2Interconnect and method of handling supplementary data in an interconnectADVANCED RISC MACH LTD·Filed 2018·Granted Feb 18, 2020·3 cites·18 claims
- 0675US2025068563A1Circuitry and MethodADVANCED RISC MACH LTD·Filed 2024·Application pending·0 cites
- 0773US10740032B2Resource allocation for atomic data access requestsADVANCED RISC MACH LTD·Filed 2018·Granted Aug 11, 2020·2 cites·15 claims
- 0872US9311244B2Enforcing ordering of snoop transactions in an interconnect for an integrated circuitADVANCED RISC MACH LTD·Filed 2014·Granted Apr 12, 2016·3 cites·19 claims
- 0972US9213660B2Receiver based communication permission token allocationADVANCED RISC MACH LTD·Filed 2013·Granted Dec 15, 2015·3 cites·19 claims
- 1069US12422992B2Increased throughput for writes to memoryADVANCED RISC MACH LTD·Filed 2024·Granted Sep 23, 2025·0 cites·20 claims
- 1168US9639470B2Coherency checking of invalidate transactions caused by snoop filter eviction in an integrated circuitADVANCED RISC MACH LTD·Filed 2014·Granted May 2, 2017·2 cites·13 claims
- 1264US10372866B2Data processing system to implement wiring/silicon blockages via parameterized cellsIBM·Filed 2017·Granted Aug 6, 2019·1 cites·20 claims
- 1364US9892072B2Transaction response modification within interconnect circuitryADVANCED RISC MACH LTD·Filed 2015·Granted Feb 13, 2018·1 cites·17 claims
- 1464US9294301B2Selecting between contending data packets to limit latency differences between sourcesTUNE ANDREW DAVID·Filed 2012·Granted Mar 22, 2016·2 cites·17 claims
- 1562US9361236B2Handling write requests for a data arrayADVANCED RISC MACH LTD·Filed 2013·Granted Jun 7, 2016·1 cites·24 claims
- 1658US11599467B2Cache for storing coherent and non-coherent dataADVANCED RISC MACH LTD·Filed 2021·Granted Mar 7, 2023·0 cites·22 claims
- 1757US2025362999A1Optimized error correction code architecture for memoryADVANCED RISC MACH LTD·Filed 2024·Application pending·0 cites
- 1857US2025363003A1Tag way-haltingADVANCED RISC MACH LTD·Filed 2024·Application pending·0 cites
- 1957US2025363051A1Optimized tag lookup in a way halting cacheADVANCED RISC MACH LTD·Filed 2024·Application pending·0 cites
- 2057US2025362816A1Method of memory access with efficient tag pipeline latencyADVANCED RISC MACH LTD·Filed 2024·Application pending·0 cites
- 2155US2025378254A1Method and System for Tracking Integrated Circuit Physical Design VerificationIBM·Filed 2024·Application pending·0 cites
- 2249US12087353B2Burst read with flexible burst length for on-chip memoryADVANCED RISC MACH LTD·Filed 2022·Granted Sep 10, 2024·0 cites·18 claims
- 2347US10796040B2Integrated circuit design and fabricationADVANCED RISC MACH LTD·Filed 2019·Granted Oct 6, 2020·0 cites·15 claims
- 2446US10169236B2Cache coherencyADVANCED RISC MACH LTD·Filed 2016·Granted Jan 1, 2019·0 cites·17 claims
- 2545US10437750B2Relative data width indication for read responses routed by an interconnectADVANCED RISC MACH LTD·Filed 2017·Granted Oct 8, 2019·0 cites·21 claims
- 2644US10938622B2Interconnection network for integrated circuit with fault detection circuitry provided locally to an upstream locationADVANCED RISC MACH LTD·Filed 2019·Granted Mar 2, 2021·0 cites·19 claims
- 2743US11023390B1Resizing circuitryADVANCED RISC MACH LTD·Filed 2020·Granted Jun 1, 2021·0 cites·19 claims
- 2843US9852088B2Hazard checking control within interconnect circuitryADVANCED RISC MACH LTD·Filed 2015·Granted Dec 26, 2017·0 cites·20 claims
- 2942US11314676B2Apparatus and method for buffered interconnectADVANCED RISC MACH LTD·Filed 2015·Granted Apr 26, 2022·0 cites·14 claims
- 3042US10255103B2Transaction handlingADVANCED RISC MACH LTD·Filed 2017·Granted Apr 9, 2019·0 cites·13 claims
- 3141US9928195B2Interconnect and method of operation of an interconnect for ordered write observation (OWO)ADVANCED RISC MACH LTD·Filed 2015·Granted Mar 27, 2018·0 cites·15 claims
- 3240US9977742B2Cache coherencyADVANCED RISC MACH LTD·Filed 2016·Granted May 22, 2018·0 cites·11 claims
- 3339US2014082215A1Arbitrating between data paths in a bufferless free flowing interconnectTUNE ANDREW DAVID·Filed 2012·Application pending·0 cites
- 3436US9170979B2Converging interconnect node controlling operation related to associated future item in dependence upon data predicted based on current transaction data item passing throughSALISBURY SEAN JAMES·Filed 2012·Granted Oct 27, 2015·0 cites·20 claims
- 3533US2010097131A1Hardening of self-timed circuits against glitchesBAINBRIDGE JOHN·Filed 2007·Application pending·0 cites
- 3631US2009009182A1Circuit to provide testability to a self-timed circuitBAINBRIDGE JOHN·Filed 2007·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →