Inventor · disambiguated record
Sergey K. Tolpygo
Also filed as: TOLPYGO SERGEY K
10 granted patents·3 pending applications·237 citations·filing 2006–2023
92Inventor score
Top patents by PatentIndex Score
13 records- 0197US9136457B2Double-masking technique for increasing fabrication yield in superconducting electronicsHYPRES INC·Filed 2013·Granted Sep 15, 2015·21 cites·20 claims
- 0297US8437818B1System and method for providing multi-conductive layer metallic interconnects for superconducting integrated circuitsHYPRES INC·Filed 2012·Granted May 7, 2013·75 cites·20 claims
- 0395US9130116B1System and method for providing multi-conductive layer metallic interconnects for superconducting integrated circuitsHYPRES INC·Filed 2013·Granted Sep 8, 2015·24 cites·20 claims
- 0494US8301214B1System and method for providing multi-conductive layer metallic interconnects for superconducting integrated circuitsTOLPYGO SERGEY K·Filed 2011·Granted Oct 30, 2012·69 cites·35 claims
- 0593US10833243B1System and method for providing multi-conductive layer metallic interconnects for superconducting integrated circuitsHYPRES INC·Filed 2017·Granted Nov 10, 2020·8 cites·20 claims
- 0693US8383426B1Double-masking technique for increasing fabrication yield in superconducting electronicsHYPRES INC·Filed 2011·Granted Feb 26, 2013·13 cites·22 claims
- 0792US9741920B1System and method for providing multi-conductive layer metallic interconnects for superconducting integrated circuitsHYPRES INC·Filed 2015·Granted Aug 22, 2017·8 cites·20 claims
- 0890US7615385B2Double-masking technique for increasing fabrication yield in superconducting electronicsHYPRES INC·Filed 2006·Granted Nov 10, 2009·14 cites·19 claims
- 0986US10109673B2Double-masking technique for increasing fabrication yield in superconducting electronicsHYPRES INC·Filed 2017·Granted Oct 23, 2018·3 cites·20 claims
- 1080US9595656B2Double-masking technique for increasing fabrication yield in superconducting electronicsHYPRES INC·Filed 2015·Granted Mar 14, 2017·2 cites·20 claims
- 1155US2009315021A1Double-masking technique for increasing fabrication yield in superconducting electronicsHYPRES INC·Filed 2008·Application pending·0 cites
- 1249US2025224441A1Two-Phase Helium Convection Loop for Cryogenic CoolingMASSACHUSETTS INST TECHNOLOGY·Filed 2022·Application pending·0 cites
- 1348US2025204281A1Process for low-loss dielectric and related structuresMASSACHUSETTS INST TECHNOLOGY·Filed 2023·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →