Double-masking technique for increasing fabrication yield in superconducting electronics

Abstract

An improved microfabrication technique for Josephson junctions in superconducting integrated circuits, based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junctions. The top layer of the mask is a resist material, and the bottom layer is a dielectric material chosen so to maximize adhesion between the resist and the underlying superconducting layer, be etch-compatible with the underlying superconducting layer, and be insoluble in the resist and anodization processing chemistries. The superconductor is preferably niobium, under a silicon dioxide layer, with a conventional photoresist or electron-beam resist as the top layer. This combination results in a substantial increase in the fabrication yield of high-density superconducting integrated circuits, increase in junction uniformity and reduction in defect density. A dry etch more compatible with microlithography may be employed.

1 . An integrated circuit having Josephson junctions, comprising:
 (a) a Josephson junction trilayer formed into circuit elements on a substrate;   (b) at least one strongly adhering adhesion layer deposited on a Josephson junction trilayer; and   (c) a patterned resist formed on top of the at least one adhesion layer, which is formed by exposing the resist to radiation to define a latent pattern therein, and selectively removing a first portion of the resist in dependence on the defined latent pattern, wherein a second portion of the resist remains on the at least one adhesion layer having a strong adhesion thereto, a portion of the at least one adhesion layer being exposed by removal of the first portion of the resist and etching through the mask thereby formed, to selectively expose portions of the Josephson junction trilayer,   wherein the Josephson junction trilayer is selectively processed after forming the patterned resist thereon to form circuit elements therefrom.   
   
   
       2 . The integrated circuit according to  claim 1 , wherein the circuit elements have minimum feature sizes less than 1.5 microns. 
   
   
       3 . The integrated circuit according to  claim 1 , wherein the circuit elements have submicron feature sizes. 
   
   
       4 . The integrated circuit according to  claim 1 , wherein the at least one adhesion layer comprises SiO 2 . 
   
   
       5 . The integrated circuit according to  claim 1 , wherein the Josephson junction trilayer comprises a niobium-based superconductor. 
   
   
       6 . The integrated circuit according to  claim 1 , wherein the resist comprises a photoresist. 
   
   
       7 . The integrated circuit according to  claim 1 , wherein the resist comprises an electron beam exposed resist. 
   
   
       8 . The integrated circuit according to  claim 1 , wherein the mask is etched by plasma etching. 
   
   
       9 . The integrated circuit according to  claim 1 , wherein the mask is etched by reactive ion etching. 
   
   
       10 . The integrated circuit according to  claim 1 , wherein the mask is etched by ion beam etching. 
   
   
       11 . The integrated circuit according to  claim 1 , wherein the at least one adhesion layer is deposited substantially without formation of pin holes therethrough. 
   
   
       12 . The integrated circuit according to  claim 1 , wherein the at least one adhesion layer is deposited by a sputtering process. 
   
   
       13 . The integrated circuit according to  claim 1 , wherein the Josephson junction circuit elements are formed by an anodization process. 
   
   
       14 . The integrated circuit according to  claim 1 , wherein the Josephson junction circuit elements are formed by a process substantially absent a wet etching step. 
   
   
       15 . The integrated circuit according to  claim 1 , wherein the Josephson junction circuit elements are formed by an anodization step adapted to convert at least a portion of the Josephson junction trilayer to an AlO x  layer over a NbO x  layer, and a portion of the converted Josephson junction trilayer is etched by ion-milling with a neutral beam of argon atoms to remove the AlO x  layer and the NbO x  layer. 
   
   
       16 . The integrated circuit according to  claim 1 , wherein the Josephson junction circuit elements are formed by an anodization step adapted to convert at least a portion of the Josephson junction trilayer to an AlO x  layer over a NbO x  layer, and a portion of the converted Josephson junction trilayer is etched by a chlorine-based plasma etching to remove the AlO x  layer, and a fluorine-based plasma is then used to remove the NbO x  layer. 
   
   
       17 . The integrated circuit according to  claim 1 , wherein the circuit elements comprise at least two separately operating Josephson junctions. 
   
   
       18 . The integrated circuit according to  claim 1 , further comprising an anodization ring formed from the Josephson junction trilayer around an active region of a circuit element. 
   
   
       19 . A superconducting integrated circuit, comprising:
 (a) a substrate;   (b) a plurality of circuit elements formed on the substrate from a Josephson junction trilayer;   (b) a patterned silicon dioxide layer formed on the Josephson junction trilayer, the patterned silicon dioxide layer being strongly adherent to a top layer of the Josephson junction trilayer; and   (c) a patterned resist formed on top of the adhesion layer, the patterned resist being strongly adherent to the adhesion layer;   wherein the patterned resist, patterned adhesion layer and plurality of circuit elements are formed by exposing an unpatterned resist to radiation to define a latent pattern therein, selectively removing a first portion of the resist in dependence on the defined latent pattern, wherein a second portion of the resist remains on the adhesion layer, a portion of the adhesion layer being exposed by removal of the first portion of the resist and etching through the mask thereby formed, to selectively expose portions of the Josephson junction trilayer, and selectively processing the exposed Josephson junction trilayer after forming the patterned resist thereon, to form the plurality of circuit elements.   
   
   
       20 . The superconducting integrated circuit according to  claim 19 , further comprising an anodization ring formed from the Josephson junction trilayer around an active region of a respective circuit element.