Inventor · disambiguated record
Shih-Chia Kao
Also filed as: KAO SHIH-CHIA
14 granted patents·401 citations·filing 2002–2013
94Inventor score
Top patents by PatentIndex Score
14 records- 0196US7058869B2Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuitsSYNTEST TECHNOLOGIES INC·Filed 2004·Granted Jun 6, 2006·119 cites·34 claims
- 0294US6954887B2Multiple-capture DFT system for scan-based integrated circuitsSYNTEST TECHNOLOGIES INC·Filed 2002·Granted Oct 11, 2005·64 cites·33 claims
- 0393US7007213B2Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-testSYNTEST TECHNOLOGIES INC·Filed 2002·Granted Feb 28, 2006·52 cites·30 claims
- 0493US6957403B2Computer-aided design system to automate scan synthesis at register-transfer levelSYNTEST TECHNOLOGIES INC·Filed 2002·Granted Oct 18, 2005·69 cites·68 claims
- 0591US7191373B2Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniquesSYNTEST TECHNOLOGIES INC·Filed 2002·Granted Mar 13, 2007·48 cites·19 claims
- 0688US7331032B2Computer-aided design system to automate scan synthesis at register-transfer levelSYNTEST TECHNOLOGIES INC·Filed 2005·Granted Feb 12, 2008·12 cites·11 claims
- 0778US7444567B2Method and apparatus for unifying self-test with scan-test during prototype debug and production testSYNTEST TECHNOLOGIES INC·Filed 2003·Granted Oct 28, 2008·17 cites·18 claims
- 0876US9057763B2Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-testSYNTEST TECHNOLOGIES INC·Filed 2013·Granted Jun 16, 2015·2 cites·98 claims
- 0976US9026875B2Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-testSYNTEST TECHNOLOGIES INC·Filed 2013·Granted May 5, 2015·2 cites·55 claims
- 1075US7779323B2Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-testSYNTEST TECHNOLOGIES INC·Filed 2008·Granted Aug 17, 2010·5 cites·21 claims
- 1168US8769359B2Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-testSYNTEST TECHNOLOGIES INC·Filed 2013·Granted Jul 1, 2014·1 cites·30 claims
- 1268US7904773B2Multiple-capture DFT system for scan-based integrated circuitsSYNTEST TECHNOLOGIES INC·Filed 2008·Granted Mar 8, 2011·4 cites·34 claims
- 1364US8543950B2Computer-aided design system to automate scan synthesis at register-transfer levelWANG LAUNG-TERNG L-T·Filed 2012·Granted Sep 24, 2013·1 cites·4 claims
- 1458US7441165B2Read-only memory and operational control method thereofPROLIFIC TECHNOLOGY INC·Filed 2005·Granted Oct 21, 2008·5 cites·6 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →