Inventor · disambiguated record
Shao-Ming Koh
Also filed as: KOH SHAO MING
18 granted patents·26 pending applications·102 citations·filing 2013–2024
93Inventor score
Top patents by PatentIndex Score
44 records- 0197US9431512B2Methods of forming nanowire devices with spacers and the resulting devicesGLOBALFOUNDRIES INC·Filed 2014·Granted Aug 30, 2016·32 cites·19 claims
- 0293US10490459B2Method for source/drain contact formation in semiconductor devicesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Nov 26, 2019·6 cites·20 claims
- 0391US11532504B2Low-resistance contact plugs and method forming sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Dec 20, 2022·2 cites·20 claims
- 0491US9306019B2Integrated circuits with nanowires and methods of manufacturing the sameGLOBALFOUNDRIES INC·Filed 2014·Granted Apr 5, 2016·12 cites·16 claims
- 0590US9660075B2Integrated circuits with dual silicide contacts and methods for fabricating sameGLOBALFOUNDRIES INC·Filed 2016·Granted May 23, 2017·5 cites·19 claims
- 0690US9196710B2Integrated circuits with relaxed silicon / germanium finsGLOBALFOUNDRIES INC·Filed 2014·Granted Nov 24, 2015·11 cites·19 claims
- 0789US11037924B2Method for forming source/drain contactsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Jun 15, 2021·4 cites·20 claims
- 0888US12009363B2Method for forming source/drain contactsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Jun 11, 2024·1 cites·20 claims
- 0988US9490340B2Methods of forming nanowire devices with doped extension regions and the resulting devicesGLOBALFOUNDRIES INC·Filed 2014·Granted Nov 8, 2016·8 cites·19 claims
- 1087US9117842B2Methods of forming contacts to source/drain regions of FinFET devicesGLOBALFOUNDRIES INC·Filed 2013·Granted Aug 25, 2015·9 cites·24 claims
- 1182US9196694B2Integrated circuits with dual silicide contacts and methods for fabricating sameGLOBALFOUNDRIES INC·Filed 2013·Granted Nov 24, 2015·5 cites·16 claims
- 1279US12068191B2Low-resistance contact plugs and method forming sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Aug 20, 2024·0 cites·20 claims
- 1379US2024332298A1Method for forming source/drain contactsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 1478US9293462B2Integrated circuits with dual silicide contacts and methods for fabricating sameGLOBALFOUNDRIES INC·Filed 2014·Granted Mar 22, 2016·3 cites·15 claims
- 1577US10741438B2Low-resistance contact plugs and method forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Aug 11, 2020·1 cites·20 claims
- 1674US9177805B2Integrated circuits with metal-insulator-semiconductor (MIS) contact structures and methods for fabricating sameGLOBALFOUNDRIES INC·Filed 2014·Granted Nov 3, 2015·3 cites·20 claims
- 1767US11217492B2Method for source/drain contact formation in semiconductor devices using common doping and common etching to n-type and p-type source/drainsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Jan 4, 2022·0 cites·20 claims
- 1867US11145554B2Method for source/drain contact formation in semiconductor devicesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Oct 12, 2021·0 cites·20 claims
- 1961US2025006787A1Integrated circuit structures having reduced end capINTEL CORP·Filed 2023·Application pending·0 cites
- 2059US10153198B2Low-resistance contact plugs and method forming sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Dec 11, 2018·0 cites·20 claims
- 2159US2025294866A1Gate cut confined within gate trenchINTEL CORP·Filed 2024·Application pending·0 cites
- 2259US2025301708A1Forksheet transistors with self-aligned dielectric spineINTEL CORP·Filed 2024·Application pending·0 cites
- 2358US2025374619A1Gated subfin reduction techniques in nanoribbon-based transistorsINTEL CORP·Filed 2024·Application pending·0 cites
- 2457US2025220986A1Airgap spacer wrapped around a contactINTEL CORP·Filed 2023·Application pending·0 cites
- 2556US2025267909A1Integrated circuit structure with direct backside source or drain contact enabled by silicon germanium etch stopINTEL CORP·Filed 2024·Application pending·0 cites
- 2656US2024312996A1Integrated circuit structures having uniform grid metal gate and trench contact plug for tub gates with pyramidal channel structuresINTEL CORP·Filed 2023·Application pending·0 cites
- 2756US2025212464A1Bilayer cavity spacer for gate-all-around transistorINTEL CORP·Filed 2023·Application pending·0 cites
- 2854US2025204042A1Backside self-aligned backbone for forksheet transistorsINTEL CORP·Filed 2023·Application pending·0 cites
- 2954US2024312986A1Integrated circuit structures having self-aligned uniform grid metal gate and trench contact plug for tub gatesINTEL CORP·Filed 2023·Application pending·0 cites
- 3054US2025220944A1Method of controlling metal gate height and selective spacer formationINTEL CORP·Filed 2023·Application pending·0 cites
- 3154US2024332290A1Transistor with channel-symmetric gateINTEL CORP·Filed 2023·Application pending·0 cites
- 3254US2024213250A1Self-aligned backbone for forksheet transistorsINTEL CORP·Filed 2022·Application pending·0 cites
- 3353US2025220991A1Integrated circuit structure with direct backside source or drain contactINTEL CORP·Filed 2023·Application pending·0 cites
- 3453US2024088218A1Gate cuts in a grating pattern across an integrated circuitINTEL CORP·Filed 2022·Application pending·0 cites
- 3553US2024204103A1Transistor gate-channel arrangements with multiple dipole materialsINTEL CORP·Filed 2022·Application pending·0 cites
- 3653US2025006810A1Transistor with channel-symmetric gateINTEL CORP·Filed 2023·Application pending·0 cites
- 3751US2024312991A1Fabrication of gate-all-around integrated circuit structures having tuned upper nanowiresINTEL CORP·Filed 2023·Application pending·0 cites
- 3851US2025220969A1Gate-all-around devices with different gate lengthsINTEL CORP·Filed 2023·Application pending·0 cites
- 3949US2024113233A1Wall coupled with two stacks of nanoribbons to electrical isolate gate metalsINTEL CORP·Filed 2022·Application pending·0 cites
- 4049US2024105589A1Integrated circuit (ic) device with metal layer including staggered metal linesINTEL CORP·Filed 2022·Application pending·0 cites
- 4149US2025105148A1Differentiated conductive lines for advanced integrated circuit structure fabricationINTEL CORP·Filed 2023·Application pending·0 cites
- 4248US2016049490A1Integrated circuits with dual silicide contacts and methods for fabricating sameGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
- 4343US2015333162A1Methods of forming nanowire devices with metal-insulator-semiconductor source/drain contacts and the resulting devicesGLOBALFOUNDRIES INC·Filed 2014·Application pending·0 cites
- 4440US2014273365A1Methods of forming contacts to source/drain regions of finfet devices by forming a region that includes a schottky barrier lowering materialGLOBALFOUNDRIES INC·Filed 2013·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →