Inventor · disambiguated record
Sharad Malik
Also filed as: MALIK SHARAD
17 granted patents·1 pending application·840 citations·filing 1992–2005
96Inventor score
Files withNEC USA INC5NEC CORP4MONTEREY DESIGN SYSTEMS3MONTEREY DESIGN SYSTEMS INC2NEC RESEARCH INST INC1
Top patents by PatentIndex Score
18 records- 0191US6286128B1Method for design optimization using logical and physical informationMONTEREY DESIGN SYSTEMS INC·Filed 1998·Granted Sep 4, 2001·202 cites·10 claims
- 0288US6961916B2Placement method for integrated circuit design using topo-clusteringSYNOPSYS INC·Filed 2002·Granted Nov 1, 2005·45 cites·7 claims
- 0387US6442743B1Placement method for integrated circuit design using topo-clusteringMONTEREY DESIGN SYSTEMS·Filed 1998·Granted Aug 27, 2002·126 cites·13 claims
- 0485US6651234B2Partition-based decision heuristics for SAT and image computation using SAT and BDDsNEC CORP·Filed 2001·Granted Nov 18, 2003·42 cites·27 claims
- 0577US6038392AImplementation of boolean satisfiability with non-chronological backtracking in reconfigurable hardwareNEC USA INC·Filed 1998·Granted Mar 14, 2000·79 cites·12 claims
- 0668US5522063AMethod of finding minimum-cost feedback-vertex sets for a graph for partial scan testing without exhaustive cycle enumerationNEC USA INC·Filed 1993·Granted May 28, 1996·27 cites·26 claims
- 0763US5448497AExploiting multi-cycle false paths in the performance optimization of sequential circuitsNEC RESEARCH INST INC·Filed 1992·Granted Sep 5, 1995·39 cites·6 claims
- 0861US7418369B2Method and system for efficient implementation of boolean satisfiabilityUNIV PRINCETON·Filed 2002·Granted Aug 26, 2008·8 cites·31 claims
- 0961US6874135B2Method for design validation using retimingNEC CORP·Filed 1999·Granted Mar 29, 2005·36 cites·12 claims
- 1061US6035109AMethod for using complete-1-distinguishability for FSM equivalence checkingNEC USA INC·Filed 1997·Granted Mar 7, 2000·39 cites·10 claims
- 1160US6247164B1Configurable hardware system implementing Boolean Satisfiability and method thereofNEC USA INC·Filed 1997·Granted Jun 12, 2001·39 cites·15 claims
- 1259US5841673ASystem and method for processing graphic delay data of logic circuit to reduce topological redundancyNEC CORP·Filed 1996·Granted Nov 24, 1998·42 cites·42 claims
- 1358US5937183AEnhanced binary decision diagram-based functional simulationNEC USA INC·Filed 1996·Granted Aug 10, 1999·33 cites·21 claims
- 1454US6367051B1System and method for concurrent buffer insertion and placement of logic gatesMONTEREY DESIGN SYSTEMS INC·Filed 1998·Granted Apr 2, 2002·31 cites·23 claims
- 1549US6192508B1Method for logic optimization for improving timing and congestion during placement in integrated circuit designMONTEREY DESIGN SYSTEMS·Filed 1998·Granted Feb 20, 2001·23 cites·18 claims
- 1643US2005149301A1Method for design validation using retimingNEC CORP·Filed 2005·Application pending·0 cites
- 1741US5457638ATiming analysis of VLSI circuitsNEC RESEARCH INSTITUE INC·Filed 1993·Granted Oct 10, 1995·16 cites·1 claims
- 1839US6449756B1Method for accurate and efficient updates of timing information logic synthesis, placement and routing for integrated circuit designMONTEREY DESIGN SYSTEMS·Filed 1998·Granted Sep 10, 2002·13 cites·23 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →