Inventor · disambiguated record
Shinsuke Yada
Also filed as: YADA SHINSUKE
33 granted patents·4 pending applications·497 citations·filing 2013–2025
97Inventor score
Top patents by PatentIndex Score
37 records- 0198US10475804B1Three-dimensional memory device containing multilevel drain select gate isolation and methods of making the sameSANDISK TECHNOLOGIES LLC·Filed 2018·Granted Nov 12, 2019·33 cites·3 claims
- 0298US10192878B1Three-dimensional memory device with self-aligned multi-level drain select gate electrodesSANDISK TECHNOLOGIES LLC·Filed 2017·Granted Jan 29, 2019·54 cites·12 claims
- 0398US9356043B1Three-dimensional memory devices containing memory stack structures with position-independent threshold voltageSANDISK TECHNOLOGIES INC·Filed 2015·Granted May 31, 2016·62 cites·21 claims
- 0498US9356034B1Multilevel interconnect structure and methods of manufacturing the sameSANDISK TECHNOLOGIES INC·Filed 2015·Granted May 31, 2016·51 cites·22 claims
- 0597US11393836B2Three-dimensional memory device with separated source-side lines and method of making the sameSANDISK TECHNOLOGIES LLC·Filed 2020·Granted Jul 19, 2022·7 cites·20 claims
- 0697US11121153B1Three-dimensional memory devices containing structures for controlling gate-induced drain leakage current and method of making the sameSANDISK TECHNOLOGIES LLC·Filed 2020·Granted Sep 14, 2021·9 cites·13 claims
- 0797US11049568B1Three-dimensional memory device with depletion region position control and method of erasing same using gate induced leakageSANDISK TECHNOLOGIES LLC·Filed 2020·Granted Jun 29, 2021·17 cites·20 claims
- 0897US10559582B2Three-dimensional memory device containing source contact to bottom of vertical channels and method of making the sameSANDISK TECHNOLOGIES LLC·Filed 2018·Granted Feb 11, 2020·24 cites·10 claims
- 0997US9449983B2Three dimensional NAND device with channel located on three sides of lower select gate and method of making thereofSANDISK TECHNOLOGIES INC·Filed 2013·Granted Sep 20, 2016·49 cites·4 claims
- 1096US10957680B2Semiconductor die stacking using vertical interconnection by through-dielectric via structures and methods for making the sameSANDISK TECHNOLOGIES LLC·Filed 2019·Granted Mar 23, 2021·18 cites·1 claims
- 1196US10381450B1Three-dimensional memory device with self-aligned drain select level isolation structures and method of making thereofSANDISK TECHNOLOGIES LLC·Filed 2018·Granted Aug 13, 2019·22 cites·9 claims
- 1296US10297610B2Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the sameSANDISK TECHNOLOGIES LLC·Filed 2017·Granted May 21, 2019·26 cites·6 claims
- 1396US10236300B2On-pitch drain select level isolation structure for three-dimensional memory device and method of making the sameSANDISK TECHNOLOGIES LLC·Filed 2017·Granted Mar 19, 2019·15 cites·13 claims
- 1496US9548313B2Method of making a monolithic three dimensional NAND string using a select gate etch stop layerSANDISK TECHNOLOGIES INC·Filed 2015·Granted Jan 17, 2017·25 cites·17 claims
- 1595US11935784B2Three-dimensional memory device containing self-aligned bit line contacts and methods for forming the sameSANDISK TECHNOLOGIES LLC·Filed 2021·Granted Mar 19, 2024·4 cites·20 claims
- 1695US10600800B2Three-dimensional memory device containing multilevel drain select gate isolation and methods of making the sameSANDISK TECHNOLOGIES LLC·Filed 2018·Granted Mar 24, 2020·15 cites·8 claims
- 1794US11501835B2Three-dimensional memory device and method of erasing thereof from a source sideSANDISK TECHNOLOGIES LLC·Filed 2021·Granted Nov 15, 2022·4 cites·19 claims
- 1893US9716062B2Multilevel interconnect structure and methods of manufacturing the sameSANDISK TECHNOLOGIES LLC·Filed 2016·Granted Jul 25, 2017·10 cites·20 claims
- 1992US10381229B2Three-dimensional memory device with straddling drain select electrode lines and method of making thereofSANDISK TECHNOLOGIES LLC·Filed 2017·Granted Aug 13, 2019·9 cites·12 claims
- 2092US9754956B2Uniform thickness blocking dielectric portions in a three-dimensional memory structureSANDISK TECHNOLOGIES INC·Filed 2014·Granted Sep 5, 2017·10 cites·13 claims
- 2191US11889684B2Three-dimensional memory device with separated source-side lines and method of making the sameSANDISK TECHNOLOGIES LLC·Filed 2020·Granted Jan 30, 2024·2 cites·18 claims
- 2291US9530787B2Batch contacts for multiple electrically conductive layersSANDISK TECHNOLOGIES INC·Filed 2014·Granted Dec 27, 2016·18 cites·11 claims
- 2387US9876027B2Three dimensional NAND device with channel located on three sides of lower select gate and method of making thereofSANDISK TECHNOLOGIES LLC·Filed 2016·Granted Jan 23, 2018·4 cites·22 claims
- 2486US10692884B2Three-dimensional memory device including bottle-shaped memory stack structures and drain-select gate electrodes having cylindrical portionsSANDISK TECHNOLOGIES LLC·Filed 2018·Granted Jun 23, 2020·4 cites·14 claims
- 2582US11758718B2Three dimensional memory device containing truncated channels and method of operating the same with different erase voltages for different bit linesSANDISK TECHNOLOGIES LLC·Filed 2021·Granted Sep 12, 2023·1 cites·20 claims
- 2679US9793288B2Methods of fabricating memory device with spaced-apart semiconductor charge storage regionsSANDISK TECHNOLOGIES INC·Filed 2014·Granted Oct 17, 2017·4 cites·19 claims
- 2762US12507414B2Three-dimensional memory device with laterally separated source select electrodes and methods of forming the sameWESTERN DIGITAL TECH INC·Filed 2023·Granted Dec 23, 2025·0 cites·20 claims
- 2861USRE49165EOn-pitch drain select level isolation structure for three-dimensional memory device and method of making the sameSANDISK TECHNOLOGIES LLC·Filed 2020·Granted Aug 9, 2022·0 cites·13 claims
- 2958US2024292627A1Memory device including an electrically conductive layer with a tapered corner and method of making the sameSANDISK TECHNOLOGIES LLC·Filed 2024·Application pending·0 cites
- 3058US2025024672A1Three-dimensional memory device including horizontal semiconductor channels and methods of forming the sameWESTERN DIGITAL TECH INC·Filed 2023·Application pending·0 cites
- 3157US2024334698A1Three-dimensional memory device including a source structure surrounded by inner sidewalls of vertical semiconductor channels and methods of forming the sameSANDISK TECHNOLOGIES LLC·Filed 2023·Application pending·0 cites
- 3256US12461692B2Select gate bias gradation structure in NAND memorySANDISK TECHNOLOGIES INC·Filed 2024·Granted Nov 4, 2025·0 cites·20 claims
- 3355US11882702B2Lateral transistors for selecting blocks in a three-dimensional memory array and methods for forming the sameSANDISK TECHNOLOGIES LLC·Filed 2021·Granted Jan 23, 2024·0 cites·19 claims
- 3454US12456521B2Sub-block separation in NAND memory through word line based selectorsSANDISK TECHNOLOGIES INC·Filed 2023·Granted Oct 28, 2025·0 cites·20 claims
- 3552US12108597B2Three-dimensional memory device containing a pillar contact between channel and source and methods of making the sameSANDISK TECHNOLOGIES LLC·Filed 2022·Granted Oct 1, 2024·0 cites·20 claims
- 3649US2025194091A1Source side select gate electrical isolation in nand memory using ion implantationSANDISK TECHNOLOGIES INC·Filed 2025·Application pending·0 cites
- 3748US11626415B2Lateral transistors for selecting blocks in a three-dimensional memory array and methods for forming the sameSANDISK TECHNOLOGIES LLC·Filed 2021·Granted Apr 11, 2023·0 cites·8 claims
Join the waitlist — get patent alerts
Get an alert when Shinsuke Yada files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →