Inventor · disambiguated record
Soo-Bong Chang
Also filed as: CHANG SOO BONG
16 granted patents·3 pending applications·66 citations·filing 2000–2024
92Inventor score
Top patents by PatentIndex Score
19 records- 0182US11961551B2Bitline sense amplifier and a memory device with an equalizerSAMSUNG ELECTRONICS CO LTD·Filed 2022·Granted Apr 16, 2024·1 cites·20 claims
- 0282US7660141B2Layout structures and methods of fabricating layout structuresSAMSUNG ELECTRONICS CO LTD·Filed 2007·Granted Feb 9, 2010·10 cites·13 claims
- 0376US12451181B2Bitline sense amplifier with equalizing transistor and a memory deviceSAMSUNG ELECTRONICS CO LTD·Filed 2024·Granted Oct 21, 2025·0 cites·18 claims
- 0473US10726886B2Memory circuits precharging memory cell arrays and memory devices including the sameSAMSUNG ELECTRONICS CO LTD·Filed 2018·Granted Jul 28, 2020·3 cites·13 claims
- 0573US7864599B2Device and method generating internal voltage in semiconductor memory deviceSAMSUNG ELECTRONICS CO LTD·Filed 2009·Granted Jan 4, 2011·7 cites·12 claims
- 0671US9620197B1Circuit for driving sense amplifier of semiconductor memory device and operating method thereofSAMSUNG ELECTRONICS CO LTD·Filed 2016·Granted Apr 11, 2017·3 cites·20 claims
- 0770US8009494B2Semiconductor memory device implementing full-VDD bit line precharge scheme using bit line sense amplifierSAMSUNG ELECTRONICS CO LTD·Filed 2009·Granted Aug 30, 2011·7 cites·24 claims
- 0870US7474549B2Bit-line equalizer, semiconductor memory device including the same, and method for manufacturing bit-line equalizerSAMSUNG ELECTRONICS CO LTD·Filed 2007·Granted Jan 6, 2009·4 cites·22 claims
- 0970US7359280B2Layout structure for sub word line drivers and method thereofSAMSUNG ELECTRONICS CO LTD·Filed 2006·Granted Apr 15, 2008·4 cites·29 claims
- 1067US7336518B2Layout for equalizer and data line sense amplifier employed in a high speed memory deviceSAMSUNG ELECTRONICS CO LTD·Filed 2006·Granted Feb 26, 2008·6 cites·20 claims
- 1157US6847536B1Semiconductor memory device having structure for preventing level of boosting voltage applied to a node from dropping and method of forming the sameSAMSUNG ELECTRONICS CO LTD·Filed 2004·Granted Jan 25, 2005·7 cites·18 claims
- 1257US6327190B1Complementary differential input buffer for a semiconductor memory deviceSAMSUNG ELECTRONICS CO LTD·Filed 2000·Granted Dec 4, 2001·10 cites·7 claims
- 1356US8189406B2Device and method generating internal voltage in semiconductor memory deviceCHANG SOO-BONG·Filed 2010·Granted May 29, 2012·2 cites·13 claims
- 1448US11881283B2Semiconductor memory device and memory system including memory cell arrays and column selection transistors arranged to improve size efficiencySAMSUNG ELECTRONICS CO LTD·Filed 2021·Granted Jan 23, 2024·0 cites·20 claims
- 1548US7352636B2Circuit and method for generating boosted voltage in semiconductor memory deviceSAMSUNG ELECTRONICS CO LTD·Filed 2005·Granted Apr 1, 2008·0 cites·9 claims
- 1639US7075849B2Semiconductor memory device and layout method thereofSAMSUNG ELECTRONICS CO LTD·Filed 2004·Granted Jul 11, 2006·2 cites·15 claims
- 1734US2012213018A1Device and method generating internal voltage in semiconductor memory deviceCHANG SOO-BONG·Filed 2012·Application pending·0 cites
- 1831US2011044121A1Semiconductor memory device having device for controlling bit line loading and improving sensing efficiency of bit line sense amplifierKIM JOUNG-YEAL·Filed 2010·Application pending·0 cites
- 1925US2006126416A1Memory cell array structure adapted to maintain substantially uniform voltage distribution across plate electrodeEUN DONG-MYUNG·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →