Inventor · disambiguated record
Sonia Ghosh
Also filed as: GHOSH SONIA
11 granted patents·2 pending applications·55 citations·filing 2010–2023
85Inventor score
Top patents by PatentIndex Score
13 records- 0197US10916275B1Write driver and pre-charge circuitry for high performance pseudo-dual port (PDP) memoriesQUALCOMM INC·Filed 2020·Granted Feb 9, 2021·16 cites·20 claims
- 0295US9685210B1Overlapping precharge and data writeQUALCOMM INC·Filed 2016·Granted Jun 20, 2017·27 cites·23 claims
- 0388US9858988B1Timing circuit for memoriesQUALCOMM INC·Filed 2016·Granted Jan 2, 2018·10 cites·24 claims
- 0483US11092646B1Determining a voltage and/or frequency for a performance modeQUALCOMM INC·Filed 2020·Granted Aug 17, 2021·2 cites·10 claims
- 0552US9484300B2Device resulting from printing minimum width semiconductor features at non-minimum pitchGLOBALFOUNDRIES INC·Filed 2015·Granted Nov 1, 2016·0 cites·7 claims
- 0649US9263349B2Printing minimum width semiconductor features at non-minimum pitch and resulting deviceGLOBALFOUNDRIES INC·Filed 2013·Granted Feb 16, 2016·0 cites·11 claims
- 0747US11289495B1Static random access memory (SRAM) bit cell circuits with a minimum distance between a storage circuit active region and a read port circuit active region to reduce area and SRAM bit cell array circuitsQUALCOMM INC·Filed 2020·Granted Mar 29, 2022·0 cites·21 claims
- 0847US2025095698A1High speed memory circuit architecture with improved area and power efficiencyQUALCOMM INC·Filed 2023·Application pending·0 cites
- 0947US2024428831A1Circuit with a low-power charge-sharing light-sleep modeQUALCOMM INC·Filed 2023·Application pending·0 cites
- 1046US11251123B1Static random access memory (SRAM) bit cells employing asymmetric width read and write word lines, and related methodsQUALCOMM INC·Filed 2020·Granted Feb 15, 2022·0 cites·20 claims
- 1146US9564375B2Structures and methods for extraction of device channel widthGLOBALFOUNDRIES INC·Filed 2013·Granted Feb 7, 2017·0 cites·18 claims
- 1232US9905316B2Efficient sense amplifier shifting for memory redundancyQUALCOMM INC·Filed 2016·Granted Feb 27, 2018·0 cites·17 claims
- 1329US8238187B2Fast cyclic decoder circuit for FIFO/LIFO data bufferJAIN ANIMESH·Filed 2010·Granted Aug 7, 2012·0 cites·25 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →