Inventor · disambiguated record
Sridhar Narayanan
Also filed as: NARAYANAN SRIDHAR
21 granted patents·1 pending application·357 citations·filing 1996–2013
96Inventor score
Top patents by PatentIndex Score
22 records- 0190US6658632B1Boundary scan cell architecture with complete set of operational modes for high performance integrated circuitsSUN MICROSYSTEMS INC·Filed 2000·Granted Dec 2, 2003·49 cites·21 claims
- 0287US8503264B1Reducing power consumption in a segmented memoryNARAYANAN SRIDHAR·Filed 2011·Granted Aug 6, 2013·13 cites·8 claims
- 0387US5881067AFlip-flop design and technique for scan chain diagnosisSUN MICROSYSTEMS INC·Filed 1997·Granted Mar 9, 1999·70 cites·19 claims
- 0483US8219946B1Method for clock gating circuitsMANOVIT CHAIYASIT·Filed 2010·Granted Jul 10, 2012·11 cites·19 claims
- 0583US8099703B1Method and system for verifying power-optimized electronic designs using equivalency checkingMANOVIT CHAIYASIT·Filed 2008·Granted Jan 17, 2012·14 cites·22 claims
- 0681US8341578B2Clock gater with test features and low setup timeCAMPBELL BRIAN J·Filed 2010·Granted Dec 25, 2012·5 cites·20 claims
- 0779US5774474APipelined scan enable for fast scan testingSUN MICROSYSTEMS INC·Filed 1996·Granted Jun 30, 1998·45 cites·18 claims
- 0876US8743653B1Reducing dynamic power consumption of a memory circuitNARAYANAN SRIDHAR·Filed 2012·Granted Jun 3, 2014·6 cites·13 claims
- 0974US7779372B2Clock gater with test features and low setup timeAPPLE INC·Filed 2007·Granted Aug 17, 2010·6 cites·15 claims
- 1072US6452423B1Circuit for avoiding contention in one-hot or one-cold multiplexer designsSUN MICROSYSTEMS INC·Filed 2000·Granted Sep 17, 2002·16 cites·14 claims
- 1171US8423935B1Method and apparatus for verifying output-based clock gatingMANOVIT CHAIYASIT·Filed 2011·Granted Apr 16, 2013·4 cites·20 claims
- 1265US6578168B1Method for operating a boundary scan cell design for high performance I/O cellsSUN MICROSYSTEMS INC·Filed 2000·Granted Jun 10, 2003·12 cites·3 claims
- 1363US5682391AApparatus and method for high speed shifting of test data through an integrated circuitSUN MICROSYSTEMS INC·Filed 1996·Granted Oct 28, 1997·25 cites·19 claims
- 1462US7746116B1Method and apparatus to clock-gate a digital integrated circuit by use of feed-forward quiescent input analysisXILINX INC·Filed 2009·Granted Jun 29, 2010·5 cites·14 claims
- 1560US5898702AMutual exclusivity circuit for use in test pattern application scan architecture circuitsSUN MICROSYSTEMS INC·Filed 1997·Granted Apr 27, 1999·23 cites·15 claims
- 1657US5983376AAutomated scan insertion flow for control block designSUN MICROSYSTEMS INC·Filed 1997·Granted Nov 9, 1999·20 cites·18 claims
- 1752US6081913AMethod for ensuring mutual exclusivity of selected signals during application of test patternsSUN MICROSYSTEMS INC·Filed 1997·Granted Jun 27, 2000·17 cites·10 claims
- 1852US2013325588A1Method and System for Measuring the Effectiveness of Search AdvertisingTRUSTEES FOR THE LELAND STANFORD JUNIOR UNIVERSITY BOARD OF·Filed 2013·Application pending·0 cites
- 1946US5896396AMethod and apparatus for scan test of SRAM for microprocessors without full scan capabilitySUN MICROSYSTEMS INC·Filed 1997·Granted Apr 20, 1999·11 cites·6 claims
- 2045US7055135B2Method for debugging an integrated circuitSUN MICROSYSTEMS INC·Filed 2002·Granted May 30, 2006·2 cites·17 claims
- 2142US6567944B1Boundary scan cell design for high performance I/O cellsSUN MICROSYSTEMS INC·Filed 2000·Granted May 20, 2003·2 cites·3 claims
- 2233US6507925B1Spatial and temporal alignment of a scan dump for debug of scan-based designsSUN MICROSYSTEMS INC·Filed 2000·Granted Jan 14, 2003·1 cites·15 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →