Inventor · disambiguated record
Sridhar Samudrala
Also filed as: SAMUDRALA SRIDHAR
28 granted patents·13 pending applications·254 citations·filing 1986–2024
96Inventor score
Files withINTEL CORP17DIGITAL EQUIPMENT CORP4HEWLETT PACKARD DEVELOPMENT CO4WIEDEMEIER JEFF3COMPAQ INFORMATION TECHNOLOGIE2
Top patents by PatentIndex Score
41 records- 0192US9513917B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2014·Granted Dec 6, 2016·10 cites·14 claims
- 0291US9778909B2Double rounded combined floating-point multiply and addINTEL CORP·Filed 2016·Granted Oct 3, 2017·7 cites·11 claims
- 0388US2024427600A1Vector friendly instruction format and execution thereofINTEL CORP·Filed 2024·Application pending·0 cites
- 0486US8667042B2Functional unit for vector integer multiply add instructionWIEDEMEIER JEFF·Filed 2010·Granted Mar 4, 2014·13 cites·14 claims
- 0584US12086594B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2023·Granted Sep 10, 2024·0 cites·23 claims
- 0684US9141386B2Vector logical reduction operation implemented using swizzling on a semiconductor chipWIEDEMEIER JEFF·Filed 2010·Granted Sep 22, 2015·10 cites·16 claims
- 0783US9477441B2Double rounded combined floating-point multiply and addINTEL CORP·Filed 2015·Granted Oct 25, 2016·3 cites·10 claims
- 0877US10037205B2Instruction and logic to provide vector blend and permute functionalityVALENTINE ROBERT·Filed 2011·Granted Jul 31, 2018·5 cites·28 claims
- 0977US9213523B2Double rounded combined floating-point multiply and addSAMUDRALA SRIDHAR·Filed 2012·Granted Dec 15, 2015·5 cites·24 claims
- 1076US11740904B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2021·Granted Aug 29, 2023·0 cites·20 claims
- 1175US10135687B2Virtual group policy based filtering within an overlay networkLENOVO ENTPR SOLUTIONS SINGAPORE PTE LTD·Filed 2014·Granted Nov 20, 2018·4 cites·15 claims
- 1275US6564239B2Computer method and apparatus for division and square root operations using signed digitHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted May 13, 2003·18 cites·48 claims
- 1373US11210096B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2020·Granted Dec 28, 2021·0 cites·28 claims
- 1472US12231339B2Extension of openvswitch megaflow offloads to hardware to address hardware pipeline limitationsINTEL CORP·Filed 2020·Granted Feb 18, 2025·1 cites·15 claims
- 1570US9329848B2Mechanism for facilitating dynamic and efficient fusion of computing instructions in software programsLUPON MARC·Filed 2013·Granted May 3, 2016·4 cites·20 claims
- 1666US10795680B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2019·Granted Oct 6, 2020·0 cites·9 claims
- 1765US9092213B2Functional unit for vector leading zeroes, vector trailing zeroes, vector operand 1s count and vector parity calculationWIEDEMEIER JEFF·Filed 2010·Granted Jul 28, 2015·2 cites·19 claims
- 1865US4849923AApparatus and method for execution of floating point operationsDIGITAL EQUIPMENT CORP·Filed 1986·Granted Jul 18, 1989·37 cites·20 claims
- 1963US7127483B2Method and system of a microprocessor subtraction-division floating point dividerHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Oct 24, 2006·10 cites·31 claims
- 2063US5317527ALeading one/zero bit detector for floating point operationDIGITAL EQUIPMENT CORP·Filed 1993·Granted May 31, 1994·45 cites·17 claims
- 2160US12170624B2Technologies that provide policy enforcement for resource accessINTEL CORP·Filed 2021·Granted Dec 17, 2024·0 cites·20 claims
- 2260US6779012B2Computer method and apparatus for division and square root operations using signed digitHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Aug 17, 2004·6 cites·21 claims
- 2358US2019108029A1Systems, apparatuses, and methods for blending two source operands into a single destination using a writemaskINTEL CORP·Filed 2018·Application pending·0 cites
- 2458US2019108030A1Systems, apparatuses, and methods for blending two source operands into a single destination using a writemaskINTEL CORP·Filed 2018·Application pending·0 cites
- 2553US2024126622A1I/o acceleration in a multi-node architectureVASUDEVAN ANIL·Filed 2023·Application pending·0 cites
- 2652US6732135B1Method and apparatus for accumulating partial quotients in a digital processorHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted May 4, 2004·3 cites·12 claims
- 2752US5341319AMethod and apparatus for controlling a rounding operation in a floating point multiplier circuitDIGITAL EQUIPMENT CORP·Filed 1993·Granted Aug 23, 1994·25 cites·14 claims
- 2851US6366942B1Method and apparatus for rounding floating point results in a digital processing systemCOMPAQ INFORMATION TECHNOLOGIE·Filed 1999·Granted Apr 2, 2002·26 cites·18 claims
- 2951US2025141794A1Programming a packet processing deviceINTEL CORP·Filed 2023·Application pending·0 cites
- 3051US2013305020A1Vector friendly instruction format and execution thereofVALENTINE ROBERT C·Filed 2011·Application pending·0 cites
- 3149US2012254588A1Systems, apparatuses, and methods for blending two source operands into a single destination using a writemaskADRIAN JESUS CORBAL SAN·Filed 2011·Application pending·0 cites
- 3248US9389871B2Combined floating point multiplier adder with intermediate rounding logicINTEL CORP·Filed 2013·Granted Jul 12, 2016·0 cites·30 claims
- 3346US2009316581A1Methods, Systems and Computer Program Products for Dynamic Selection and Switching of TCP Congestion Control Algorithms Over a TCP ConnectionIBM·Filed 2008·Application pending·0 cites
- 3446US2019391940A1Technologies for interrupt disassociated queuing for multi-queue i/o devicesINTEL CORP·Filed 2019·Application pending·0 cites
- 3543US2004186874A1Method and apparatus for accumulating partial quotients in a digital processorFiled 2004·Application pending·0 cites
- 3642US2021326177A1Queue scaling based, at least, in part, on processing loadINTEL CORP·Filed 2021·Application pending·0 cites
- 3740US6360241B1Computer method and apparatus for division and square root operations using signed digitCOMPAQ INFORMATION TECHNOLOGIE·Filed 1999·Granted Mar 19, 2002·10 cites·4 claims
- 3839US2012254592A1Systems, apparatuses, and methods for expanding a memory source into a destination register and compressing a source register into a destination memory locationSAN ADRIAN JESUS CORBAL·Filed 2011·Application pending·0 cites
- 3935US4852039AApparatus and method for accelerating floating point addition and subtraction operations by accelerating the effective subtraction procedureDIGITAL EQUIPMENT CORP·Filed 1987·Granted Jul 25, 1989·8 cites·20 claims
- 4033US2018150654A1Techniques for a Field Programmable Gate Array to Perform a Function for an Application Specific Integrated CircuitINTEL CORP·Filed 2016·Application pending·0 cites
- 4130US6144228AGeneralized push-pull cascode logic techniqueCOMPAQ COMPUTER CORP·Filed 1999·Granted Nov 7, 2000·2 cites·42 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →