Vector friendly instruction format and execution thereof

Abstract

A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

1 - 19 . (canceled) 
     
     
         20 . An apparatus comprising:
 a processor configured to execute an instruction set, wherein the instruction set includes a first instruction format, wherein the first instruction format has a plurality of fields including a class field, an alpha field, and a beta field, wherein the first instruction format supports different augmentation operations through placement of different values in the alpha field and the beta field, wherein only one of the different values may be placed in each of the alpha field and the beta field on each occurrence of an instruction in the first instruction format in instruction streams, the processor including,
 a decode unit to decode the occurrences of the instructions in the first instruction format with the class field's content specifying a first class as follows:
 distinguish, for each of the occurrences that does not specify memory access, whether to augment with a round type operation or not based on the alpha field's content in that occurrence, wherein the beta field is interpreted as a suppress all floating point exceptions (SAE) field and a round operation field when the alpha field's content indicates the round type operation; 
 distinguish, for each of the occurrences that does not specify memory access and that does specify the round type operation through the alpha field's content, whether floating point exceptions will be suppressed or not based on the SAE field's content in that occurrence; and 
 distinguish, for each of the occurrences that does not specify memory access and that does specify the round type operation through the alpha field's content, which one of a plurality of round operations to apply based on the round operation field's content in that occurrence. 
 
   
     
     
         21 . The apparatus of  claim 20 , wherein the plurality of round operations includes round to nearest, round down, round up, and round toward zero. 
     
     
         22 . The apparatus of  claim 20 , wherein the decode unit is also to decode the occurrences of the instructions in the first instruction format with the class field's content specifying a second class as follows:
 interpret, for each of the occurrences that does not specify memory access, the beta field as including an RL field;   distinguish, for each of the occurrences that does not specify memory access, whether to augment with a round type operation or with a vector length type operation based on the RL field's content in that occurrence, wherein a remainder of the beta field is interpreted as a round operation field when the RL field's content indicates the round type operation, and wherein the remainder of the beta field is instead interpreted as a vector length field when the RL field's content indicates the vector length type operation;   distinguish, for each of the occurrences that does not specify memory access and that does specify the round type operation through the RL field's content, which one of the plurality of round operations to apply based on the beta field's content and its interpretation as the round operation field in that occurrence.   
     
     
         23 . The apparatus of  claim 22 , wherein, for each of the occurrences that does not specify memory access and that does specify the round type operation through the RL field's content, floating point exceptions are suppressed. 
     
     
         24 . The apparatus of  claim 22 , wherein the decode unit is also to decode the occurrences of the instructions in the first instruction format with the class field's content specifying the second class as follows:
 distinguish, for each of the occurrences that does not specify memory access and that does specify the vector length type operation through the RL field's content, which one of a plurality of vector lengths to use based on the beta field's content and its interpretation as the vector length field in that occurrence.   
     
     
         25 . The apparatus of  claim 24 , wherein the plurality of vector lengths includes 128, 256, and 512 bits. 
     
     
         26 . The apparatus of  claim 20 , wherein length of vector operated on by the first class is 512 bits. 
     
     
         27 . The processor of  claim 20 , wherein the first instruction format further includes a data element width field, wherein the first instruction format supports through different values in the data element width field the specification of different data element widths. 
     
     
         28 . The processor of  claim 27 , wherein the first instruction format supports through different values in the data element width field the specification of a 32 bit and a 64 bit data element width for the first class. 
     
     
         29 . An apparatus comprising:
 a processor configured to execute an instruction set, wherein the instruction set includes a first instruction format, wherein the first instruction format includes a first plurality of templates, wherein the first instruction format has a plurality of fields including a base operation field, a data element width (W) field, and a write mask field, wherein the first instruction format supports through different values in the base operation field the specification of different vector operations, wherein each of the vector operations generates a destination vector operand including a plurality of data elements at different data element positions, wherein the first instruction format supports through different values in the data element width field the specification of different data element widths, wherein the base operation field, the data element width field, and the write mask field may each store only one value on each occurrence of an instruction in the first instruction format in instruction streams, the processor including,
 a decode unit to decode the occurrences of the instructions in the first plurality of templates as follows:
 distinguish, for each of the occurrences, which one of the data element widths to use based on the data element width field's content; and 
 distinguish, for each of the occurrences, which of the data elements resulting from the occurrence's vector operation is or is not to be reflected in the destination vector operand's corresponding data element positions based on the write mask field's content and the data element width for that occurrence, wherein one of the different values that may be placed in the write mask field is reserved for indicating that all of the results of the occurrence's vector operation are to be reflected in the destination vector operand's corresponding data element positions, wherein others of the different values that may be placed in the write mask field distinguish different write mask registers storing configurable write masks, and wherein the data element width for the occurrence distinguishes which data element positions correspond with which bits of the configurable write masks. 
 
   
     
     
         30 . The apparatus of  claim 29 , wherein the first instruction format supports through different values in the data element width field the specification of a 32 bit and a 64 bit data element width. 
     
     
         31 . The apparatus of  claim 29 , wherein the write mask registers are at least 64 bits. 
     
     
         32 . The apparatus of  claim 29 , wherein the destination vector operands generated by the different vector operations are 512 bits. 
     
     
         33 . The apparatus of  claim 29 , wherein a single bit of the write mask is used for each of the data element positions of the destination vector operand. 
     
     
         34 . The apparatus of  claim 29 , wherein the lower 16 bits of the write mask register is used for 512 bit vectors with 32 bit data elements, and the lower 8 bits of the write mask register is used for 512 bit vectors with 32 bit data elements. 
     
     
         35 . The apparatus of  claim 29 , wherein at least certain of the different vector operations operate on two source operands and the destination vector operand does not overwrite either of the two source operands. 
     
     
         36 . The apparatus of  claim 29 , wherein at least certain of the different vector operations operate on two source operands and the destination vector operand overwrites one of the two source operands. 
     
     
         37 . The apparatus of  claim 29 , wherein the data elements in the destination vector operand's data element positions that are to not reflect the occurrence's vector operation are preserved. 
     
     
         38 . An apparatus comprising:
 a processor configured to execute an instruction set, wherein the instruction set includes a first instruction format, wherein the first instruction format includes a first plurality of templates that each include a plurality of fields including a base operation field, a data element width (W) field, a vector length field, and a write mask field, wherein the first instruction format supports through different values in the base operation field the specification of a plurality of different vector operations, wherein each of the plurality of vector operations requires an operation to be independently performed on each of a plurality of different data element positions of at least one source vector operand to generate at least one destination vector operand, wherein the first instruction format supports through different values in the data element width field the specification of a 32 bit and a 64 bit data element width, wherein the first plurality of templates support through different values in the vector length field the specification of a plurality of different vector lengths, wherein the first instruction format supports through different values in the write mask field the specification of different write masks, wherein only one of the different values may be placed in each of the base operation field, the data element width field, and the write mask field on each occurrence of an instruction in the first instruction format in instruction streams, the processor including,
 a decode unit to decode the occurrences of the instructions in the first plurality of templates as follows:
 distinguish, for each of the occurrences, which one of the different vector operations to perform based on the base operation field's content; 
 distinguish, for each of the occurrences, which one of the data element widths to use based on the data element width field's content; 
 distinguish, for each of the occurrences, which one of the vector lengths to use based on the vector length field's content; and 
 distinguish, for each of the occurrences, which one of the different write masks to use based on the write mask field's content, wherein the data element width and the vector length for the occurrence distinguishes which data element positions correspond with which bits of the occurrence's write mask, and wherein the write mask for the occurrence specifies on a per data element position basis whether the results of the occurrence's vector operation is or is not to be reflected in the destination vector operand's corresponding data element positions. 
 
   
     
     
         39 . The apparatus of  claim 38 , wherein the plurality of different vector lengths includes 128, 256, and 512 bits. 
     
     
         40 . The apparatus of  claim 38 , wherein the first instruction format also supports through different values in the data element width field the specification of an 8 bit and a 16 bit data element width. 
     
     
         41 . The apparatus of  claim 38 , wherein the first instruction format also supports through different values in a real opcode field inside the base operation field the specification of an 8 bit and a 16 bit data element width. 
     
     
         42 . The apparatus of  claim 38 , wherein the first instruction format supports a zeroing-writemasking operation. 
     
     
         43 . The apparatus of  claim 38 , wherein one of the different values that may be placed in the write mask field is reserved for indicating that all of the results of the occurrence's vector operation are to be reflected in the destination vector operand's corresponding data element positions. 
     
     
         44 . The apparatus of  claim 38 , wherein others of the different values that may be placed in the write mask field distinguish different write mask registers storing configurable write masks. 
     
     
         45 . The apparatus of  claim 38 , wherein the first instruction format supports operations on two source vector operands and the destination vector operand does not overwrite either of the two source vector operands. 
     
     
         46 . The apparatus of  claim 38 , wherein the first instruction format supports operations on two source vector operands and the destination vector operand overwrites one of the two source vector operands. 
     
     
         47 - 56 . (canceled) 
     
     
         57 . An apparatus comprising:
 a processor configured to execute an instruction set, wherein the instruction set includes a first instruction format, wherein the first instruction format has a plurality of fields including a base operation field, a modifier field, a data element width field, and an augmentation operation field, wherein the first instruction format supports through different values in the base operation field the specification of a plurality of different vector operations, wherein each of the plurality of vector operations generates a destination vector operand having a plurality of data elements at different data element positions, wherein the first instruction format supports through different values in the modifier field the specification of memory access and no memory access operations, wherein the first instruction format includes a displacement factor field when the modifier field's content specifies a memory access operation with scaled displacement, wherein the base operation field, the modifier field, the data element width field, and the augmentation operation field may each stored only one value on each occurrence of an instruction in the first instruction format, the processor including,
 a processor pipeline to execute the instructions in the first instruction format occurring in instruction streams, wherein the pipeline is configured to:
 distinguish the occurrences of instructions in the first instruction format that specify memory access with scaled displacement from those that do not based on the modifier field's content in those different occurrences; 
 distinguish, for the occurrences that specify memory access with scaled displacement through the modifier field's content, between a plurality of memory access sizes based on the contents of two or more of the base operation field, the data element width field, and the augmentation operation field; and 
 determine, for each of the occurrences that specifies memory access with scaled displacement through the modifier field's content, a scaled displacement based on multiplying the size of the memory access by the displacement factor field's content, wherein the scaled displacement is to be used to generate an address. 
 
   
     
     
         58 . The apparatus of  claim 57 , wherein the first instruction format also supports the modifier field's content specifying unscaled displacement and no displacement. 
     
     
         59 . The apparatus of  claim 57 , wherein the first instruction format includes a displacement field when the modifier field's content specifies a memory access operation with unscaled displacement. 
     
     
         60 . The apparatus of  claim 57 , wherein a scale, an index, and a base are pulled from fields of the first instruction format when the modifier field's content specifies a memory access operation with scaled displacement, and wherein the scale, index, base, and scaled displacement are used to generate the address. 
     
     
         61 . The apparatus of  claim 60 , wherein the scale is pulled from a two bit scale field, the index is pulled from a combination of a one bit X field and a three bit XXX field, and the base is pulled from a combination of a one bit B field and a three bit BBB. 
     
     
         62 . The apparatus of  claim 57 , wherein the selection of fields used to distinguish between the plurality of memory access sizes is based on the content of a class field within the augmentation operation field. 
     
     
         63 . The apparatus of  claim 62 , wherein, when the class field's content specifies a first class, the fields used to distinguish between the plurality of memory access sizes include two or more of the base operation field, a data manipulation field within the augmentation operation field, and the data element width field. 
     
     
         64 . The apparatus of  claim 62 , wherein, when the class field's content specifies a second class, the fields used to distinguish between the plurality of memory access sizes include two or more of the base operation field, a broadcast field within the augmentation operation field, a vector length field within the augmentation operation field, and the data element width field. 
     
     
         65 . The apparatus of  claim 57 , wherein the displacement factor field is a single byte. 
     
     
         66 . The apparatus of  claim 65 , wherein the displacement factor field's content is interpreted as a signed value between −128 and 127. 
     
     
         67 . The apparatus of  claim 57 , wherein the plurality of memory access sizes correspond to the number of bytes in the memory access. 
     
     
         68 . The apparatus of  claim 57 , wherein the plurality of memory access sizes are 1 byte, 2 bytes, 4 bytes, 8 bytes, 16 bytes, 32 bytes, and 64 bytes. 
     
     
         69 - 77 . (canceled) 
     
     
         78 . An apparatus comprising:
 a processor including:
 a plurality of architectural vector registers that are each at least 512 bits in size, 
 a plurality of architectural write mask registers that are at least 64 bits in size to store configurable write masks, 
   wherein the processor is configured to execute an instruction set, wherein the instruction set includes a plurality of instruction formats including a vector friendly instruction format, wherein vector instructions in the vector friendly instruction format specify vector operations that generate a destination vector operand having a plurality of data elements at different data element positions, wherein the vector friendly instruction format includes the following fields of the following size and in the following order,
 a one byte format field to store a value that uniquely identifies the vector friendly instruction format; 
 a one bit R field to store a bit that is combined with a first set of three lower order bits to address the architectural vector registers for certain instructions in the vector friendly instruction format; 
 a one bit X field to store a bit that is combined with a second set of three lower order bits to address the architectural vector registers for certain instructions in the vector friendly instruction format; 
 a one bit B field to store a bit that is combined with a third set of three lower order bits to address the architectural vector registers for certain instructions in the vector friendly instruction format; 
 a one bit R′ field to store a bit that is added as the most significant bit to the combination of the R field's bit and the first set of three lower order bits to address the architectural vector registers for certain instructions in the vector friendly instruction format; 
 a four bit opcode map that is part of a base operation field; 
 a one bit data element width (W) field to store a bit to distinguish between a 32 bit data element size and a 64 bit data element size for certain instructions in the vector friendly instruction format; 
 a four bit V field to store a low order four bits used to address the architectural vector registers for certain instructions in the vector friendly instruction format; 
 a one bit class (U) field to store a bit used to distinguish between two classes of instruction templates; 
 a two bit prefix encoding field that is part of the base operation field; 
 a one bit alpha field that is interpreted as a round type operation field, a data transform type operation field, an eviction hint field, a write mask control field, or reserved field, wherein the write mask control field's content selects between merging write mask and zeroing write mask; 
 a three bit beta field that is interpreted as a full round control field, a data transform field, or a data manipulation field depending on a modifier field's content and the alpha field's content when the class field's content indicates a first class, and is interpreted to include a two bit round operation field, a two bit vector length field or a two bit vector length field followed by a broadcast field for certain instructions in the vector friendly instruction format when the class field's content indicate a second class; 
 a one bit V′ field to store a bit that is added as the most significant bit to the four bits of the V field to address the architectural vector registers for certain instructions in the vector friendly instruction format; 
 a three bit write mask field to store different values that all address different ones of the architectural write mask registers with the exception of one that is reserved, wherein each of the configurable write masks specifies on a per data element position basis whether the results of the vector instruction's vector operation is or is not to be reflected in the destination vector operand's corresponding data element positions, whereas the one reserved value is for indicating that all of the results of the vector instruction's vector operation are to be reflected in the destination vector operand's corresponding data element positions; 
 a one byte real opcode field to store a byte that is part of the base operation field, wherein in the base operation field's content distinguishes between different base operations; and 
 the modifier field to store two bits used to distinguish between operations that require a memory access and operations that do not. 
   
     
     
         79 . The apparatus of  claim 78 , wherein the full round control field includes,
 a one bit suppress all floating point exceptions (SAE) field to store a bit used to distinguish between suppressing all floating point exceptions and not; and   a two bit round operation field to store two bits to distinguish between a plurality of different rounding operations.   
     
     
         80 . The apparatus of  claim 78 , wherein, when the three bit beta field is interpreted to include either the two bit round operation field or the two bit vector length field, the three bit beta field is interpreted to include a one bit RL field to store a bit used to distinguish when to use the two bit round operation field and the two bit vector length field. 
     
     
         81 . The apparatus of  claim 78 , wherein the vector friendly instruction format also includes the following fields of the following size and in the following order after the modifier field:
 a three bit MODR/M.reg field,   a three bit MODR/M.r/m field.   
     
     
         82 . The apparatus of  claim 81 , wherein the vector friendly instruction format also includes the following fields of the following size and in the following order after the MODR/M.r/m field when the modifier field's content indicates a memory access operation with scaled displacement:
 a two bit scale field;   a three bit XXX field;   a three bit BBB field; and   an 8 bit displacement factor field.   
     
     
         83 . The apparatus of  claim 82 , wherein a scale, an index, and a base are pulled respectively from the two bit scale field, a combination of the one bit X field and the three bit XXX field, and a combination of the one bit B field and the three bit BBB field, a scaled displacement is generated based on multiplying the size of a memory access by the displacement factor field's content, and wherein the scale, index, base, and scaled displacement are used to generate an address for the memory access. 
     
     
         84 . The apparatus of  claim 83 , wherein the address is generated by 2 scale +the index+the base+the scaled displacement. 
     
     
         85 . The apparatus of  claim 78 , wherein there are eight of the architectural write mask registers. 
     
     
         86 . The apparatus of  claim 78 , wherein there are 32 of the architectural vector registers. 
     
     
         87 . An apparatus comprising:
 a processor configured to execute an instruction set, wherein the instruction set includes a first instruction format, wherein the first instruction format has a plurality of fields including a base operation field, a modifier field, a class field, an alpha field, and a beta field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the class field, the alpha field, and the beta field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the class field, the alpha field, and the beta field on each occurrence of an instruction in the first instruction format in instruction streams, wherein a first value in the class field specifies a first class and a second value specifies a second class, the processor including,
 a decode unit to decode the occurrences of the instructions in the first instruction format with the class field's content specifying the second class as follows:
 distinguish the occurrences of instructions in the first instruction format that specify memory access from those that do not based on the modifier field's content in those different occurrences, wherein the beta field is interpreted as a broadcast field and a vector length field when the modifier field's content specifies memory access, wherein part of the beta field is interpreted as an RL field when the modifier field's content do not specify memory access; 
 distinguish, for each of the occurrences that specifies memory access through the modifier field's content, whether to broadcast or not and which one of a plurality of vector lengths to use based on the beta field's content and its interpretation as the broadcast field and the vector length field in that occurrence; and 
 distinguish, for each of the occurrences that does not specify memory access through the modifier field's content, whether to augment with a round type operation or with a vector length type operation based on the RL field's content in that occurrence, wherein a remainder of the beta field is interpreted as a round operation field when the RL field's content indicates the round type operation, and wherein the remainder of the beta field is instead interpreted as the vector length field when the RL field's content indicates the vector length type operation; 
 distinguish, for each of the occurrences that does not specify memory access through the modifier field's content and that does specify the round type operation through the RL field's content, which one of a plurality of round operations to apply based on the beta field's content and its interpretation as the round operation field in that occurrence; and 
 distinguish, for each of the occurrences, whether to perform a merging write mask operation or a zeroing write mask operation based on the alpha field's content and its interpretation as a write mask control field in that occurrence. 
 
   
     
     
         88 . The apparatus of  claim 87 , wherein the plurality of round operations includes round to nearest, round down, round up, and round toward zero. 
     
     
         89 . The apparatus of  claim 87 , wherein the first instruction format further includes a data element width field, wherein the first instruction format supports through different values in the data element width field the specification of different data element widths. 
     
     
         90 . The apparatus of  claim 89 , wherein the different data element widths include 32 bits and 64 bits. 
     
     
         91 . The apparatus of  claim 89 , wherein the first instruction format also supports through different values in a real opcode field inside the base operation field the specification of an 8 bit and a 16 bit data element width. 
     
     
         92 . The apparatus of  claim 89 , wherein the first instruction format further includes a real opcode field inside the base operation field, wherein the real opcode field's content distinguishes whether the data element width field's content selects between a 64 bit and a 32 bit data element size or selects between a 16 bit and an 8 bit data element size for each of the occurrences. 
     
     
         93 . The apparatus of  claim 87 , wherein the plurality of vector lengths include 128 bits, 256 bits, and 512 bits. 
     
     
         94 . The apparatus of  claim 87 , wherein the broadcast operation includes 1-element granularity broadcast. 
     
     
         95 . The apparatus of  claim 87 , wherein at least certain of the different base operations operate on two source operands and the destination operand does not overwrite either of the two source operands. 
     
     
         96 . The apparatus of  claim 87 , wherein at least certain of the different base operations operate on two source operands and the destination operand overwrites one of the two source operands. 
     
     
         97 . The apparatus of  claim 87 , wherein the second class supports the modifier field's content specifying a memory access operation with a scaled displacement, in which case the first instruction format includes a displacement factor field and fields from which a scale, an index, and a base are pulled, wherein the scaled displacement is generated based on multiplying the size of a memory access by the displacement factor field's content, and wherein the scale, index, base, and scaled displacement are used to generate an address for the memory access. 
     
     
         98 . The apparatus of  claim 97 , wherein the address is generated by 2 scale +the index+the base+the scaled displacement. 
     
     
         99 . The apparatus of  claim 97 , wherein the displacement factor field's content is interpreted as a signed value between −128 and 127. 
     
     
         100 . The apparatus of  claim 97 , wherein the supported sizes of the memory access are 1 byte, 2 bytes, 4 bytes, 8 bytes, 16 bytes, 32 bytes, and 64 bytes. 
     
     
         101 . An apparatus comprising:
 a processor configured to execute an instruction set, wherein the instruction set includes a first instruction format, wherein the first instruction format includes a first plurality of templates, wherein the first instruction format has a plurality of fields including a base operation field, an alpha field, a data element width (W) field, and a write mask field, wherein the first instruction format supports through different values in the base operation field the specification of different vector operations, wherein each of the vector operations generates a destination vector operand including a plurality of data elements at different data element positions, wherein the first instruction format supports through different values in the data element width field the specification of different data element widths, wherein the base operation field, the alpha field, the data element width field, and the write mask field may each store only one value on each occurrence of an instruction in the first instruction format in instruction streams, the processor including,
 a decode unit to decode the occurrences of the instructions in the first plurality of templates as follows:
 distinguish, for each of the occurrences, which one of the data element widths to use based on the data element width field's content, 
 distinguish, for each of the occurrences, whether to perform a merge write mask operation or a zeroing write mask operation based on the alpha field's content and its interpretation as a write mask control field; 
 distinguish, for each of the occurrences, which of the data elements resulting from the occurrence's vector operation is or is not to be reflected in the destination vector operand's corresponding data element positions based on the write mask field's content and the data element width for the occurrence, wherein one of the different values that may be placed in the write mask field is reserved for indicating that all of the results of the occurrence's vector operation are to be reflected in the destination vector operand's corresponding data element positions, wherein others of the different values that may be placed in the write mask field distinguish different write mask registers storing configurable write masks, and wherein the data element width for the occurrence distinguishes which data element positions correspond with which bits of the configurable write masks. 
 
   
     
     
         102 . The apparatus of  claim 101 , wherein there are seven of the write mask registers for storing configuration write masks. 
     
     
         103 . The apparatus of  claim 101 , wherein the first instruction format supports through different values in the data element width field the specification of an 8 bit, a 16 bit, a 32 bit and a 64 bit data element width. 
     
     
         104 . The apparatus of  claim 101 , wherein a single bit of the write mask is used for each of the data element positions of the destination vector operand. 
     
     
         105 . The apparatus of  claim 101 , wherein at least certain of the different vector operations operate on two source operands and the destination vector operand does not overwrite either of the two source operands. 
     
     
         106 . The apparatus of  claim 101 , wherein at least certain of the different vector operations operate on two source operands and the destination vector operand overwrites one of the two source operands. 
     
     
         107 . The apparatus of  claim 101 , wherein the first instruction format further includes a real opcode field inside the base operation field, wherein the real opcode field's content distinguishes whether the data element width field's content selects between a 64 bit and a 32 bit data element size or selects between a 16 bit and an 8 bit data element size for each of the occurrences. 
     
     
         108 . An apparatus comprising:
 a processor configured to execute an instruction set, wherein the instruction set includes a first instruction format, wherein the first instruction format has a plurality of fields including a base operation field, a modifier field, and a beta field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, and the beta field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, and the beta field on each occurrence of an instruction in the first instruction format, the processor including,
 a decode unit to decode a plurality of instructions in the first instruction format, wherein the decode unit is configured to decode the plurality of instructions in the first instruction format as follows:
 distinguish those of the plurality of instructions that specify memory access from those that do not based on the modifier field's content in those different instructions, wherein part of the beta field is interpreted as an RL field when the modifier field's content does not specify memory access; 
 distinguish, for each of the plurality of instructions that does not specify memory access through the modifier field's content, whether to augment with a round type operation or with a vector length type operation based on the RL field's content in that instruction, wherein a remainder of the beta field is interpreted as a round operation field when the RL field's content indicates the round type operation, and wherein the remainder of the beta field is instead interpreted as a vector length field when the RL field's content indicates the vector length type operation; 
 distinguish, for each of the plurality of instructions that does not specify memory access through the modifier field's content and that does specify the round type operation through the RL field's content, which one of a plurality of round operations to apply based on the beta field's content and its interpretation as the round operation field in that instruction; and 
 distinguish, for each of the plurality of instructions that does not specify memory access through the modifier field's content and that does specify the vector length type operation through the RL field's content, which one of a plurality of vector lengths to use based on the beta field's content and its interpretation as the vector length field in that instruction. 
 
   
     
     
         109 . The apparatus of  claim 108 , wherein the plurality of round operations includes round to nearest, round down, round up, and round toward zero. 
     
     
         110 . The apparatus of  claim 108 , wherein the plurality of vector lengths includes 128 bits, 256 bits, and 512 bits. 
     
     
         111 . The apparatus of  claim 108 , wherein, for each of the instructions that does not specify memory access through the modifier field's content and that does specify the round type operation through the RL field's content, all floating point exceptions are suppressed. 
     
     
         112 . The apparatus of  claim 108 , wherein the first instruction format further includes a data element width field, and the contents of two or more of the data element width field, the base operation field, and the vector length field determine a memory access size, the memory access size being used to specify memory access. 
     
     
         113 . The apparatus of  claim 108 , wherein at least certain of the different versions of the base operations operate on two source operands and generates a destination operand that does not overwrite either of the two source operands. 
     
     
         114 . The apparatus of  claim 108 , wherein at least certain of the different versions of the base operations operate on two source operands and generates a destination operand that overwrites one of the two source operands. 
     
     
         115 . The apparatus of  claim 108 , wherein the first instruction format further includes a data element width field, wherein the first instruction format supports through different values in the data element width field the specification of different data element widths. 
     
     
         116 . The apparatus of  claim 115 , wherein the different data element widths include 32 bits and 64 bits. 
     
     
         117 . The apparatus of  claim 115 , wherein the first instruction format also supports through different values in a real opcode field inside the base operation field the specification of an 8 bit and a 16 bit data element width. 
     
     
         118 . The apparatus of  claim 115 , wherein the first instruction format further includes a real opcode field inside the base operation field, wherein the real opcode field's content distinguishes whether the data element width field's content selects between a 64 bit and a 32 bit data element size or selects between a 16 bit and an 8 bit data element size for each of the occurrences. 
     
     
         119 - 128 . (canceled)