Inventor · disambiguated record
Dennis R. Bradford
Also filed as: BRADFORD DENNIS · BRADFORD DENNIS R · BRADFORD DENNIS RYAN
33 granted patents·13 pending applications·145 citations·filing 2006–2025
96Inventor score
Top patents by PatentIndex Score
46 records- 0197US11093277B2Systems, methods, and apparatuses for heterogeneous computingINTEL CORP·Filed 2020·Granted Aug 17, 2021·6 cites·25 claims
- 0297US10649772B2Method and apparatus for efficient matrix transposeINTEL CORP·Filed 2018·Granted May 12, 2020·29 cites·18 claims
- 0397US10146535B2Systems, apparatuses, and methods for chained fused multiply addINTEL CORP·Filed 2016·Granted Dec 4, 2018·23 cites·22 claims
- 0496US11693691B2Systems, methods, and apparatuses for heterogeneous computingINTEL CORP·Filed 2021·Granted Jul 4, 2023·4 cites·11 claims
- 0596US11487541B2Systems, apparatuses, and methods for chained fused multiply addINTEL CORP·Filed 2020·Granted Nov 1, 2022·4 cites·34 claims
- 0695US11593295B2Apparatuses, methods, and systems for operations in a configurable spatial acceleratorINTEL CORP·Filed 2021·Granted Feb 28, 2023·6 cites·24 claims
- 0795US11200186B2Apparatuses, methods, and systems for operations in a configurable spatial acceleratorINTEL CORP·Filed 2018·Granted Dec 14, 2021·11 cites·24 claims
- 0892US9513917B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2014·Granted Dec 6, 2016·10 cites·14 claims
- 0991US11416281B2Systems, methods, and apparatuses for heterogeneous computingINTEL CORP·Filed 2016·Granted Aug 16, 2022·4 cites·28 claims
- 1090US12135981B2Systems, methods, and apparatuses for heterogeneous computingINTEL CORP·Filed 2023·Granted Nov 5, 2024·1 cites·20 claims
- 1188US2024427600A1Vector friendly instruction format and execution thereofINTEL CORP·Filed 2024·Application pending·0 cites
- 1287US10853065B2Systems, apparatuses, and methods for chained fused multiply addINTEL CORP·Filed 2018·Granted Dec 1, 2020·3 cites·22 claims
- 1387US10133577B2Vector mask driven clock gating for power efficiency of a processorINTEL CORP·Filed 2012·Granted Nov 20, 2018·8 cites·24 claims
- 1486US10268539B2Apparatus and method for multi-bit error detection and correctionINTEL CORP·Filed 2015·Granted Apr 23, 2019·7 cites·25 claims
- 1584US12086594B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2023·Granted Sep 10, 2024·0 cites·23 claims
- 1683US2025060963A1Systems, apparatuses, and methods for chained fused multiply addINTEL CORP·Filed 2024·Application pending·0 cites
- 1782US12254061B2Apparatuses and methods to accelerate matrix multiplicationINTEL CORP·Filed 2018·Granted Mar 18, 2025·3 cites·25 claims
- 1882US2025123881A1Systems, methods, and apparatuses for heterogeneous computingINTEL CORP·Filed 2024·Application pending·0 cites
- 1979US8082418B2Method and apparatus for coherent device initialization and accessSTILLWELL JR PAUL M·Filed 2007·Granted Dec 20, 2011·10 cites·16 claims
- 2077US12073214B2Systems, apparatuses, and methods for chained fused multiply addINTEL CORP·Filed 2022·Granted Aug 27, 2024·0 cites·23 claims
- 2176US11740904B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2021·Granted Aug 29, 2023·0 cites·20 claims
- 2276US9152382B2Reducing power consumption in a fused multiply-add (FMA) unit responsive to input data valuesINTEL CORP·Filed 2012·Granted Oct 6, 2015·3 cites·23 claims
- 2375US12487927B2Remote cache invalidationAPPLE INC·Filed 2024·Granted Dec 2, 2025·0 cites·18 claims
- 2474US10817291B2Apparatuses, methods, and systems for swizzle operations in a configurable spatial acceleratorINTEL CORP·Filed 2019·Granted Oct 27, 2020·2 cites·24 claims
- 2574US9323500B2Reducing power consumption in a fused multiply-add (FMA) unit responsive to input data valuesHICKMANN BRIAN·Filed 2013·Granted Apr 26, 2016·5 cites·16 claims
- 2673US11210096B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2020·Granted Dec 28, 2021·0 cites·28 claims
- 2767US2025232002A1Apparatuses and methods to accelerate matrix multiplicationINTEL CORP·Filed 2025·Application pending·0 cites
- 2866US10795680B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2019·Granted Oct 6, 2020·0 cites·9 claims
- 2966US10678541B2Processors having fully-connected interconnects shared by vector conflict instructions and permute instructionsFORSYTH ANDREW THOMAS·Filed 2011·Granted Jun 9, 2020·3 cites·18 claims
- 3066US8473715B2Dynamic accelerator reconfiguration via compiler-inserted initialization message and configuration address and size informationSTILLWELL JR PAUL M·Filed 2011·Granted Jun 25, 2013·2 cites·12 claims
- 3163US9785436B2Apparatus and method for efficient gather and scatter operationsINTEL CORP·Filed 2012·Granted Oct 10, 2017·1 cites·26 claims
- 3258US2019108029A1Systems, apparatuses, and methods for blending two source operands into a single destination using a writemaskINTEL CORP·Filed 2018·Application pending·0 cites
- 3358US2019108030A1Systems, apparatuses, and methods for blending two source operands into a single destination using a writemaskINTEL CORP·Filed 2018·Application pending·0 cites
- 3455US9606847B2Enabling error detecting and reporting in machine check architectureINTEL CORP·Filed 2014·Granted Mar 28, 2017·0 cites·20 claims
- 3551US2013305020A1Vector friendly instruction format and execution thereofVALENTINE ROBERT C·Filed 2011·Application pending·0 cites
- 3649US9804842B2Method and apparatus for efficiently managing architectural register state of a processorINTEL CORP·Filed 2014·Granted Oct 31, 2017·0 cites·20 claims
- 3749US2012254588A1Systems, apparatuses, and methods for blending two source operands into a single destination using a writemaskADRIAN JESUS CORBAL SAN·Filed 2011·Application pending·0 cites
- 3848US9842046B2Processing memory access instructions that have duplicate memory indicesINTEL CORP·Filed 2012·Granted Dec 12, 2017·0 cites·26 claims
- 3947US10719320B2Power noise injection to control rate of change of currentINTEL CORP·Filed 2017·Granted Jul 21, 2020·0 cites·20 claims
- 4046US10423421B2Opportunistic utilization of redundant ALUINTEL CORP·Filed 2012·Granted Sep 24, 2019·0 cites·22 claims
- 4145US9696992B2Apparatus and method for performing a check to optimize instruction flowINTEL CORP·Filed 2014·Granted Jul 4, 2017·0 cites·25 claims
- 4241US2012254593A1Systems, apparatuses, and methods for jumps using a mask registerSAN ADRIAN JESUS CORBAL·Filed 2011·Application pending·0 cites
- 4341US2016041827A1Instructions for merging mask patternsCORBAL JESUS·Filed 2011·Application pending·0 cites
- 4438US2009089475A1Low latency interface between device driver and network interface cardCHITLUR NAGABHUSHAN·Filed 2007·Application pending·0 cites
- 4537US2008052463A1Method and apparatus to implement cache-coherent network interfacesCHITLUR NAGABHUSHAN·Filed 2006·Application pending·0 cites
- 4633US2012254589A1System, apparatus, and method for aligning registersCORBAL SAN ADRIAN JESUS·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →