System, apparatus, and method for aligning registers

Abstract

Embodiments of systems, apparatuses, and methods for performing an align instruction in a computer processor are described. In some embodiments, the execution of an align instruction causes the selective storage of data elements of two concatenated sources to be stored in a destination.

1 . A method of performing an align instruction in a computer processor, comprising:
 fetching the align instruction, wherein the align instruction includes a writemask operand, a destination operand, a first source operand, a second source operand, and an offset value;   decoding the fetched align instruction;   executing the decoded align instruction by
 concatenating a first plurality of data elements of the first source operand and a second plurality of data elements of the second source operand, 
 shifting right the concatenated data elements based on the offset value, and 
 determining which of the right shifted, concatenated data elements are to be stored into corresponding position of the destination based on corresponding bits of the writemask; and 
   storing those data elements of the right shifted, concatenated data elements that have been determined should be stored into the destination at the corresponding position in the destination.   
     
     
         2 . The method of  claim 1 , wherein the writemask is a 16-bit register. 
     
     
         3 . The method of  claim 1 , wherein the offset is an 8-bit immediate value. 
     
     
         4 . The method of  claim 1 , further comprising:
 determining if the writemask is to be used; and   if the writemask is not to be used, storing the data elements of the right shifted, concatenated data elements at the corresponding locations of the destination without determining which of the right shifted, concatenated data elements are to be stored into corresponding position of the destination based on corresponding bits of the writemask.   
     
     
         5 . The method of  claim 1 , wherein the determining is done for each bit position of the writemask in parallel. 
     
     
         6 . The method of  claim 1 , wherein the first and second source operands are 512-bit registers. 
     
     
         7 . The method of  claim 1 , wherein the second source operand is a 512-bit memory location and the data elements from that memory location are loaded into a temporary 512-bit register prior to the concatenation of the sources. 
     
     
         8 . The method of  claim 1 , wherein the data elements of the first operand are the least significant data elements of the right shifted, concatenated data elements. 
     
     
         9 . A method, comprising:
 in response to an align instruction that includes a first and second source operand, a destination operand, a writemask operand, and an offset,
 concatenating a first set of data elements of the first source with a second set of data elements of the second source; 
 right shifting the concatenated data elements by X data elements, wherein X is an immediate value provided in the align instruction; and 
 for a first bit position of a writemask, determining if that the first bit position indicates that the corresponding data element of the shifted, concatenated data elements is to be stored in a corresponding location in the destination,
 storing the corresponding data element of the shifted, concatenated data elements is to be stored in a corresponding location in the destination when the first bit position of the writemask indicates that it should be stored, and 
 leaving a data element in the corresponding location in the destination alone when the first bit position of the writemask indicates that its corresponding data element should not be stored in the destination. 
 
   
     
     
         10 . The method of  claim 9 , further comprising:
 concatenating a first set of data elements of the first source with a second set of data elements of the second source;   for a second bit position of a writemask, determining if that the second bit position indicates that the corresponding data element of the shifted, concatenated data elements is to be stored in a corresponding location in the destination,
 storing the corresponding data element of the shifted, concatenated data elements is to be stored in a corresponding location in the destination when the second bit position of the writemask indicates that it should be stored, and 
 leaving a data element in the corresponding location in the destination alone when the second bit position of the writemask indicates that its corresponding data element should not be stored in the destination. 
   
     
     
         11 . The method of  claim 10 , further comprising:
 determining when the last bit position has been evaluated to determine if its corresponding data element of the shifted, concatenated data elements is to be stored in a corresponding location in the destination to complete the align instruction.   
     
     
         12 . The method of  claim 9 , wherein the first bit position of the writemask is the least significant bit of the writemask. 
     
     
         13 . The method of  claim 9 , wherein the writemask is a 16-bit register. 
     
     
         14 . The method of  claim 9 , wherein the offset is an 8-bit immediate value. 
     
     
         15 . The method of  claim 9 , wherein the determining is done for each bit position of the writemask in parallel. 
     
     
         16 . The method of  claim 1 , wherein the first and second source operands are 512-bit registers. 
     
     
         17 . The method of  claim 1 , wherein the second source operand is a 512-bit memory location and the data elements from that memory location are loaded into a temporary 512-bit register prior to the concatenation of the sources. 
     
     
         18 . An apparatus comprising;
 a hardware decoder to decode an align instruction, wherein the align instruction includes a writemask operand, a destination operand, a first source operand, a second source operand, and an offset value;   execution logic to
 concatenate a first plurality of data elements of the first source operand and a second plurality of data elements of the second source operand, 
 shift right the concatenated data elements based on the offset value, 
 determining which of the right shifted, concatenated data elements are to be stored into corresponding position of the destination based on corresponding bits of the writemask, and 
 store those data elements of the right shifted, concatenated data elements that have been determined should be stored into the destination at the corresponding position in the destination. 
   
     
     
         19 . The apparatus of  claim 18 , further comprising:
 a 16-bit writemask register to store the writemask; and   at least two 512-bit registers to store the data elements of the first and second sources.