Inventor · disambiguated record
Suleyman Sair
Also filed as: SAIR SULEYMAN
25 granted patents·9 pending applications·86 citations·filing 2011–2024
94Inventor score
Top patents by PatentIndex Score
34 records- 0192US9513917B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2014·Granted Dec 6, 2016·10 cites·14 claims
- 0289US10318291B2Providing vector horizontal compare functionality within a vector registerINTEL CORP·Filed 2017·Granted Jun 11, 2019·6 cites·19 claims
- 0389US9411583B2Vector instruction for presenting complex conjugates of respective complex numbersSAIR SULEYMAN·Filed 2011·Granted Aug 9, 2016·18 cites·20 claims
- 0488US9747101B2Gather-op instruction to duplicate a mask and perform an operation on vector elements gathered via tracked offset-based gatheringOULD-AHMED-VALL ELMOUSTAPHA·Filed 2011·Granted Aug 29, 2017·11 cites·30 claims
- 0588US2024427600A1Vector friendly instruction format and execution thereofINTEL CORP·Filed 2024·Application pending·0 cites
- 0685US9804844B2Instruction and logic to provide stride-based vector load-op functionality with mask duplicationOULD-AHMED-VALL ELMOUSTAPHA·Filed 2011·Granted Oct 31, 2017·9 cites·30 claims
- 0785US9448794B2Instruction and logic to provide vector horizontal majority voting functionalityOULD-AHMED-VALL ELMOUSTAPHA·Filed 2011·Granted Sep 20, 2016·7 cites·27 claims
- 0884US12086594B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2023·Granted Sep 10, 2024·0 cites·23 claims
- 0984US10248488B2Fault tolerance and detection by replication of input data and evaluating a packed data execution resultINTEL CORP·Filed 2015·Granted Apr 2, 2019·4 cites·13 claims
- 1083US9864602B2Packed rotate processors, methods, systems, and instructionsOULD-AHMED-VALL ELMOUSTAPHA·Filed 2011·Granted Jan 9, 2018·8 cites·22 claims
- 1182US9575757B2Efficient zero-based decompressionOULD-AHMED-VALL ELMOUSTAPHA·Filed 2011·Granted Feb 21, 2017·7 cites·15 claims
- 1280US9672036B2Instruction and logic to provide vector loads with strides and masking functionalityOULD-AHMED-VALL ELMOUSTAPHA·Filed 2011·Granted Jun 6, 2017·6 cites·30 claims
- 1376US11740904B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2021·Granted Aug 29, 2023·0 cites·20 claims
- 1473US11210096B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2020·Granted Dec 28, 2021·0 cites·28 claims
- 1566US10795680B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2019·Granted Oct 6, 2020·0 cites·9 claims
- 1657US10467185B2Apparatus and method of mask permute instructionsINTEL CORP·Filed 2017·Granted Nov 5, 2019·0 cites·24 claims
- 1756US10324718B2Packed rotate processors, methods, systems, and instructionsINTEL CORP·Filed 2018·Granted Jun 18, 2019·0 cites·19 claims
- 1856US9928063B2Instruction and logic to provide vector horizontal majority voting functionalityINTEL CORP·Filed 2016·Granted Mar 27, 2018·0 cites·21 claims
- 1953US2017357514A1Instruction and logic to provide vector scatter-op and gather-op functionalityINTEL CORP·Filed 2017·Application pending·0 cites
- 2051US9632980B2Apparatus and method of mask permute instructionsOULD-AHMED-VALL ELMOUSTAPHA·Filed 2011·Granted Apr 25, 2017·0 cites·20 claims
- 2151US2013305020A1Vector friendly instruction format and execution thereofVALENTINE ROBERT C·Filed 2011·Application pending·0 cites
- 2248US10241792B2Vector frequency expand instructionOULD AHMED VALL ELMOUSTAPHA·Filed 2011·Granted Mar 26, 2019·0 cites·21 claims
- 2347US10540177B2Efficient zero-based decompressionINTEL CORP·Filed 2017·Granted Jan 21, 2020·0 cites·15 claims
- 2446US9459866B2Vector frequency compress instructionOULD-AHMED-VALL ELMOUSTAPHA·Filed 2011·Granted Oct 4, 2016·0 cites·20 claims
- 2545US9665371B2Providing vector horizontal compare functionality within a vector registerOULD-AHMED-VALL ELMOUSTAPHA·Filed 2011·Granted May 30, 2017·0 cites·22 claims
- 2642US2013326192A1Broadcast operation on mask registerOULD-AHMED-VALL ELMOUSTAPHA·Filed 2011·Application pending·0 cites
- 2741US10083032B2System, apparatus and method for generating a loop alignment count or a loop alignment maskSAIR SULEYMAN·Filed 2011·Granted Sep 25, 2018·0 cites·17 claims
- 2841US9946541B2Systems, apparatuses, and method for strided accessOULD AHMED VALL ELMOUSTAPHA·Filed 2015·Granted Apr 17, 2018·0 cites·6 claims
- 2941US2017269935A1Instruction and logic to provide vector loads and stores with strides and masking functionalityOULD-AHMED-VALL ELMOUSTAPHA·Filed 2017·Application pending·0 cites
- 3040US10152321B2Instructions and logic for blend and permute operation sequencesINTEL CORP·Filed 2015·Granted Dec 11, 2018·0 cites·20 claims
- 3140US2014189296A1System, apparatus and method for loop remainder mask instructionOULD-AHMED-VALL ELMOUSTAPHA·Filed 2011·Application pending·0 cites
- 3240US2018239725A1Persistent Remote Direct Memory AccessINTEL CORP·Filed 2017·Application pending·0 cites
- 3333US2017177355A1Instruction and Logic for Permute SequenceINTEL CORP·Filed 2015·Application pending·0 cites
- 3433US2017177345A1Instruction and Logic for Permute with Out of Order LoadingINTEL CORP·Filed 2015·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Suleyman Sair files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →