Inventor · disambiguated record
Stefan Graef
Also filed as: GRAEF STEFAN
25 granted patents·734 citations·filing 1996–2009
97Inventor score
Top patents by PatentIndex Score
25 records- 0194US6714828B2Method and system for designing a probe cardFORMFACTOR INC·Filed 2001·Granted Mar 30, 2004·97 cites·54 claims
- 0287US7092902B2Automated system for designing and testing a probe cardFORMFACTOR INC·Filed 2004·Granted Aug 15, 2006·26 cites·11 claims
- 0383US6189131B1Method of selecting and synthesizing metal interconnect wires in integrated circuitsLSI LOGIC CORP·Filed 1998·Granted Feb 13, 2001·103 cites·20 claims
- 0481US6546538B1Integrated circuit having on-chip capacitors for supplying power to portions of the circuit requiring high-transient peak powerLSI LOGIC CORP·Filed 2000·Granted Apr 8, 2003·41 cites·13 claims
- 0580US7593872B2Method and system for designing a probe cardFORMFACTOR INC·Filed 2006·Granted Sep 22, 2009·6 cites·16 claims
- 0680US6305001B1Clock distribution network planning and method thereforLSI LOGIC CORP·Filed 1998·Granted Oct 16, 2001·86 cites·54 claims
- 0778US5974248AIntermediate test file conversion and comparisonLSI LOGIC CORP·Filed 1996·Granted Oct 26, 1999·41 cites·20 claims
- 0877US6101329ASystem for comparing counter blocks and flag registers to determine whether FIFO buffer can send or receive dataLSI LOGIC CORP·Filed 1997·Granted Aug 8, 2000·75 cites·25 claims
- 0974US6634014B1Delay/load estimation for use in integrated circuit designLSI LOGIC CORP·Filed 2000·Granted Oct 14, 2003·20 cites·20 claims
- 1074US6083269ADigital integrated circuit design system and methodology with hardwareLSI LOGIC CORP·Filed 1997·Granted Jul 4, 2000·72 cites·18 claims
- 1172US6532576B1Cell interconnect delay library for integrated circuit designLSI LOGIC CORP·Filed 2001·Granted Mar 11, 2003·17 cites·16 claims
- 1271US7930219B2Method and system for designing a probe cardFORMFACTOR INC·Filed 2009·Granted Apr 19, 2011·1 cites·19 claims
- 1368US6184711B1Low impact signal buffering in integrated circuitsLSI LOGIC CORP·Filed 1998·Granted Feb 6, 2001·23 cites·14 claims
- 1467US6131151AProcessing high-speed digital datastreams with reduced memoryLSI LOGIC CORP·Filed 1997·Granted Oct 10, 2000·34 cites·17 claims
- 1566US6766499B1Buffer cell insertion and electronic design automationLSI LOGIC CORP·Filed 2001·Granted Jul 20, 2004·11 cites·18 claims
- 1657US6598213B1Static timing analysis validation tool for ASIC coresLSI LOGIC CORP·Filed 2001·Granted Jul 22, 2003·5 cites·16 claims
- 1757US6064220ASemiconductor integrated circuit failure analysis using magnetic imagingLSI LOGIC CORP·Filed 1997·Granted May 16, 2000·20 cites·20 claims
- 1855US6502230B1Circuit modelingLSI LOGIC CORP·Filed 2001·Granted Dec 31, 2002·7 cites·25 claims
- 1954US6457160B1Iterative prediction of circuit delaysLSI LOGIC CORP·Filed 2000·Granted Sep 24, 2002·6 cites·21 claims
- 2049US5831993AMethod and apparatus for scan chain with reduced delay penaltyLSI LOGIC CORP·Filed 1997·Granted Nov 3, 1998·14 cites·12 claims
- 2142US6037796ACurrent waveform analysis for testing semiconductor devicesLSI LOGIC CORP·Filed 1997·Granted Mar 14, 2000·9 cites·22 claims
- 2238US5898705AMethod for detecting bus shorts in semiconductor devicesLSI LOGIC CORP·Filed 1996·Granted Apr 27, 1999·10 cites·15 claims
- 2334US6102962AMethod for estimating quiescent current in integrated circuitsLSI LOGIC CORP·Filed 1997·Granted Aug 15, 2000·6 cites·20 claims
- 2430US6687661B1Utilizing a technology-independent system description incorporating a metal layer dependent attributeLSI LOGIC CORP·Filed 1998·Granted Feb 3, 2004·1 cites·30 claims
- 2527US5771267ABurn-in activity monitorLSI LOGIC CORP·Filed 1996·Granted Jun 23, 1998·3 cites·14 claims
Join the waitlist — get patent alerts
Get an alert when Stefan Graef files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →