Inventor · disambiguated record
Stewart Logie
Also filed as: LOGIE STEWART · LOGIE STEWART G · LOGIE STEWART GORDON
19 granted patents·2 pending applications·392 citations·filing 1988–2019
94Inventor score
Files withLATTICE SEMICONDUCTOR CORP12ADVANCED MICRO DEVICES INC4VANTIS CORP3JIANG CHUN1MEHTA SUNIL1
Top patents by PatentIndex Score
21 records- 0193US6064595AFloating gate memory apparatus and method for selected programming thereofVANTIS CORP·Filed 1998·Granted May 16, 2000·123 cites·24 claims
- 0289US4924278AEEPROM using a merged source and control gateADVANCED MICRO DEVICES INC·Filed 1988·Granted May 8, 1990·63 cites·8 claims
- 0388US6294809B1Avalanche programmed floating gate memory cell structure with program element in polysiliconVANTIS CORP·Filed 1998·Granted Sep 25, 2001·60 cites·28 claims
- 0481US9672935B2Memory circuit having non-volatile memory cell and methods of usingLATTICE SEMICONDUCTOR CORP·Filed 2015·Granted Jun 6, 2017·5 cites·23 claims
- 0578US5742542ANon-volatile memory cells using only positive charge to store dataADVANCED MICRO DEVICES INC·Filed 1995·Granted Apr 21, 1998·46 cites·16 claims
- 0676US6841447B1EEPROM device having an isolation-bounded tunnel capacitor and fabrication processLATTICE SEMICONDUCTOR CORP·Filed 2002·Granted Jan 11, 2005·16 cites·19 claims
- 0773US7024646B2Electrostatic discharge simulationLATTICE SEMICONDUCTOR CORP·Filed 2004·Granted Apr 4, 2006·18 cites·22 claims
- 0873US6570212B1Complementary avalanche injection EEPROM cellLATTICE SEMICONDUCTOR CORP·Filed 2000·Granted May 27, 2003·19 cites·14 claims
- 0970US6627947B1Compact single-poly two transistor EEPROM cellLATTICE SEMICONDUCTOR CORP·Filed 2000·Granted Sep 30, 2003·16 cites·6 claims
- 1069US7989911B1Shallow trench isolation (STI) with trench liner of increased thicknessLATTICE SEMICONDUCTOR CORP·Filed 2009·Granted Aug 2, 2011·3 cites·18 claims
- 1160US7985656B1Shallow trench isolation (STI) with trench liner of increased thicknessLATTICE SEMICONDUCTOR CORP·Filed 2009·Granted Jul 26, 2011·1 cites·5 claims
- 1256US6215700B1PMOS avalanche programmed floating gate memory cell structureVANTIS CORP·Filed 1999·Granted Apr 10, 2001·16 cites·24 claims
- 1351US6660579B1Zero power memory cell with improved data retentionLATTICE SEMICONDUCTOR CORP·Filed 2002·Granted Dec 9, 2003·4 cites·17 claims
- 1445USRE48625EMemory circuit having non-volatile memory cell and methods of usingLATTICE SEMICONDUCTOR CORP·Filed 2018·Granted Jul 6, 2021·0 cites·23 claims
- 1543US2007267715A1Shallow trench isolation (STI) with trench liner of increased thicknessMEHTA SUNIL·Filed 2006·Application pending·0 cites
- 1641USRE48570EMemory circuit having non-volatile memory cell and methods of usingLATTICE SEMICONDUCTOR CORP·Filed 2019·Granted May 25, 2021·0 cites·48 claims
- 1740US2007111403A1Polycide fuse with reduced programming timeJIANG CHUN·Filed 2005·Application pending·0 cites
- 1839US6737702B1Zero power memory cell with reduced threshold voltageLATTICE SEMICONDUCTOR CORP·Filed 2003·Granted May 18, 2004·0 cites·9 claims
- 1935US7067883B2Lateral high-voltage junction deviceLATTICE SEMICONDUCTOR CORP·Filed 2003·Granted Jun 27, 2006·0 cites·5 claims
- 2032US5956610AMethod and system for providing electrical insulation for local interconnect in a logic circuitADVANCED MICRO DEVICES INC·Filed 1997·Granted Sep 21, 1999·2 cites·9 claims
- 2130US6303949B2Method and system for providing electrical insulation for local interconnect in a logic circuitADVANCED MICRO DEVICES INC·Filed 1999·Granted Oct 16, 2001·0 cites·6 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →