Shallow trench isolation (STI) with trench liner of increased thickness

Abstract

Improved shallow trench isolation (STI) techniques are provided for semiconductor devices. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a substrate, a first trench in the substrate, and a second trench in the substrate. A first silicon dioxide liner substantially lines the first trench. A second silicon dioxide liner substantially lines the second trench, wherein the second silicon dioxide liner has a thickness greater than a thickness of the first silicon dioxide liner. A silicon nitride liner is on the first silicon dioxide liner in the first trench but not on the second silicon dioxide liner in the second trench. A dielectric material fills the first and second trenches.

1 . An integrated circuit comprising:
 a substrate;   a first trench in the substrate;   a second trench in the substrate;   a first silicon dioxide liner substantially lining the first trench;   a second silicon dioxide liner substantially lining the second trench, wherein the second silicon dioxide liner has a thickness greater than a thickness of the first silicon dioxide liner;   a silicon nitride liner on the first silicon dioxide liner in the first trench but not on the second silicon dioxide liner in the second trench; and   a dielectric material filling the first and second trenches.   
   
   
       2 . The integrated circuit of  claim 1 , wherein the second silicon dioxide liner comprises a plurality of rounded corners. 
   
   
       3 . The integrated circuit of  claim 1 , wherein the silicon nitride layer is on substantially the entire first silicon dioxide liner in the first trench. 
   
   
       4 . The integrated circuit of  claim 1 , wherein the silicon nitride layer is on substantially only half the first silicon dioxide liner in the first trench. 
   
   
       5 . The integrated circuit of  claim 1 , wherein the substrate further comprises a transistor region adjacent to the first trench, wherein the transistor region is adapted to receive a low voltage transistor. 
   
   
       6 . The integrated circuit of  claim 1 , wherein the substrate further comprises a transistor region adjacent to the second trench, wherein the transistor region is adapted to receive a high voltage transistor. 
   
   
       7 . The integrated circuit of  claim 1 , wherein the substrate comprises a transistor region adjacent to the second trench, wherein the transistor region is adapted to receive a flash memory cell. 
   
   
       8 . The integrated circuit of  claim 1 , wherein the integrated circuit is a programmable logic device (PLD). 
   
   
       9 . An integrated circuit comprising:
 a substrate;   a trench in the substrate;   a silicon dioxide liner substantially lining the trench, the liner having a first portion and a second portion, wherein the first portion of the silicon dioxide liner is thinner than the second portion of the silicon dioxide liner;   a silicon nitride liner on the first portion of the silicon dioxide liner but not on the second portion;   a dielectric material filling the trench;   a first transistor region in the substrate and adjacent to a first side of the trench; and   a second transistor region in the substrate and adjacent to a second side of the trench, wherein the trench is adapted to isolate the first transistor region from the second transistor region.   
   
   
       10 . The integrated circuit of  claim 9 , wherein the first and second portions of the silicon dioxide liner are substantially equal in width. 
   
   
       11 . The integrated circuit of  claim 9 , wherein the dielectric material is silicon dioxide. 
   
   
       12 . The integrated circuit of  claim 9 , wherein the first transistor region is adapted to receive a low voltage transistor. 
   
   
       13 . The integrated circuit of  claim 9 , wherein the second transistor region is adapted to receive a high voltage transistor. 
   
   
       14 . The integrated circuit of  claim 9 , wherein the second transistor region is adapted to receive a flash memory cell. 
   
   
       15 . The integrated circuit of  claim 9 , wherein the integrated circuit is a programmable logic device (PLD). 
   
   
       16 . A method of manufacturing an integrated circuit, the method comprising:
 etching first and second trenches adjacent to high and low voltage transistor regions of a substrate, respectively;   oxidizing a silicon dioxide layer substantially lining the first and second trenches;   depositing a silicon nitride layer on the silicon dioxide layer in the first and second trenches;   etching the silicon nitride layer from the first trench but not the second trench;   increasing a thickness of the silicon dioxide layer in the first trench; and   filling the first and second trenches with a dielectric material.   
   
   
       17 . The method of  claim 16 , wherein the increasing further comprises rounding a plurality of corners of a silicon dioxide liner in the first trench formed by the silicon dioxide layer. 
   
   
       18 . The method of  claim 16 , further comprising providing a low voltage transistor in the low voltage transistor region. 
   
   
       19 . The method of  claim 16 , further comprising providing a high voltage transistor in the high voltage transistor region. 
   
   
       20 . The method of  claim 16  including concurrently with the prior steps:
 etching a third trench, the third trench separated from the first trench by the high voltage transistor region and separated from the second trench by the low voltage transistor region;   oxidizing a silicon dioxide layer substantially lining the third trench;   depositing a silicon nitride layer on the silicon dioxide layer in the third trench;   etching the silicon nitride layer only from a first portion of the third trench adjacent to the high voltage transistor region;   increasing a thickness of the silicon dioxide layer only in the first portion of the third trench; and   filling the third trench with the dielectric material.