Inventor · disambiguated record
Stephen Lee Smith
Also filed as: SMITH STEPHEN · SMITH STEPHEN L · SMITH STEPHEN LEE
36 granted patents·1 pending application·573 citations·filing 1979–2019
98Inventor score
Top patents by PatentIndex Score
37 records- 0196US4727309ACurrent difference current sourceINTEL CORP·Filed 1987·Granted Feb 23, 1988·103 cites·16 claims
- 0295US9727675B2Parameter extraction of DFTSYNOPSYS INC·Filed 2016·Granted Aug 8, 2017·14 cites·24 claims
- 0394US4791326ACurrent controlled solid state switchINTEL CORP·Filed 1987·Granted Dec 13, 1988·86 cites·10 claims
- 0494US4437171AECL Compatible CMOS memoryINTEL CORP·Filed 1982·Granted Mar 13, 1984·56 cites·18 claims
- 0590US4689504AHigh voltage decoderMOTOROLA INC·Filed 1985·Granted Aug 25, 1987·65 cites·5 claims
- 0689US10049173B2Parameter extraction of DFTSYNOPSYS INC·Filed 2017·Granted Aug 14, 2018·4 cites·20 claims
- 0788US11068631B2First principles design automation toolSYNOPSYS INC·Filed 2019·Granted Jul 20, 2021·4 cites·18 claims
- 0887US10831957B2Simulation scaling with DFT and non-DFTSYNOPSYS INC·Filed 2018·Granted Nov 10, 2020·3 cites·12 claims
- 0987US4289982AApparatus for programming a dynamic EPROMMOTOROLA INC·Filed 1979·Granted Sep 15, 1981·24 cites·12 claims
- 1085US10776560B2Mapping intermediate material properties to target properties to screen materialsSYNOPSYS INC·Filed 2019·Granted Sep 15, 2020·3 cites·15 claims
- 1185US9881111B2Simulation scaling with DFT and non-DFTSYNOPSYS INC·Filed 2014·Granted Jan 30, 2018·5 cites·22 claims
- 1285US9836563B2Iterative simulation with DFT and non-DFTSYNOPSYS INC·Filed 2014·Granted Dec 5, 2017·5 cites·10 claims
- 1382US10102318B2Atomic scale grid for modeling semiconductor structures and fabrication processesSYNOPSYS INC·Filed 2017·Granted Oct 16, 2018·2 cites·74 claims
- 1481US10489212B2Adaptive parallelization for multi-scale simulationSYNOPSYS INC·Filed 2014·Granted Nov 26, 2019·5 cites·21 claims
- 1580US9530027B2Device lock for transitSHAHIDZADEH SHAHROKH·Filed 2012·Granted Dec 27, 2016·12 cites·16 claims
- 1678US10606968B2Atomic scale grid for modeling semiconductor structures and fabrication processesSYNOPSYS INC·Filed 2018·Granted Mar 31, 2020·1 cites·17 claims
- 1778US9852242B2Atomic scale grid for modeling semiconductor structures and fabrication processesSYNOPSYS INC·Filed 2014·Granted Dec 26, 2017·3 cites·54 claims
- 1877US10516725B2Characterizing target material properties based on properties of similar materialsSYNOPSYS INC·Filed 2014·Granted Dec 24, 2019·4 cites·34 claims
- 1977US5600581ALogarithm/inverse-logarithm converter utilizing linear interpolation and method of using sameMOTOROLA INC·Filed 1995·Granted Feb 4, 1997·42 cites·26 claims
- 2075US10402520B2First principles design automation toolSYNOPSYS INC·Filed 2014·Granted Sep 3, 2019·3 cites·30 claims
- 2171US4267501ANMOS Voltage reference generatorMOTOROLA INC·Filed 1979·Granted May 12, 1981·19 cites·9 claims
- 2270US10417373B2Estimation of effective channel length for FinFETs and nano-wiresSYNOPSYS INC·Filed 2014·Granted Sep 17, 2019·2 cites·21 claims
- 2370US4968903ACombinational static CMOS logic circuitMOTOROLA INC·Filed 1989·Granted Nov 6, 1990·19 cites·8 claims
- 2467US4237547AProgram decoder for shared contact epromMOTOROLA INC·Filed 1979·Granted Dec 2, 1980·12 cites·9 claims
- 2563US5553012AExponentiation circuit utilizing shift means and method of using sameMOTOROLA INC·Filed 1995·Granted Sep 3, 1996·38 cites·39 claims
- 2660US11249813B2Adaptive parallelization for multi-scale simulationSYNOPSYS INC·Filed 2019·Granted Feb 15, 2022·0 cites·24 claims
- 2759US10685156B2Multi-scale simulation including first principles band structure extractionSYNOPSYS INC·Filed 2016·Granted Jun 16, 2020·0 cites·40 claims
- 2857US10706209B2Estimation of effective channel length for FinFETs and nano-wiresSYNOPSYS INC·Filed 2019·Granted Jul 7, 2020·0 cites·20 claims
- 2955US2016162625A1Mapping Intermediate Material Properties To Target Properties To Screen MaterialsSYNOPSYS INC·Filed 2014·Application pending·0 cites
- 3054US10756212B2FinFET with heterojunction and improved channel controlSYNOPSYS INC·Filed 2018·Granted Aug 25, 2020·0 cites·25 claims
- 3149US4464736AIn-package E2 PROM redundancyMOTOROLA INC·Filed 1982·Granted Aug 7, 1984·7 cites·7 claims
- 3248US10121896B2FinFet with heterojunction and improved channel controlSYNOPSYS INC·Filed 2015·Granted Nov 6, 2018·0 cites·16 claims
- 3341US6259720B1Versatile digital signal processing systemMOTOROLA INC·Filed 1996·Granted Jul 10, 2001·11 cites·21 claims
- 3441US5726924AExponentiation circuit utilizing shift means and method of using sameMOTOROLA INC·Filed 1996·Granted Mar 10, 1998·11 cites·16 claims
- 3532US5752012AComputational array with self timed computational element and method of self timed calculationMOTOROLA INC·Filed 1996·Granted May 12, 1998·3 cites·24 claims
- 3632US5608663AComputational array circuit for providing parallel multiplicationMOTOROLA INC·Filed 1995·Granted Mar 4, 1997·5 cites·18 claims
- 3730US5852730AHybrid instruction set for versatile digital signal processing systemFiled 1996·Granted Dec 22, 1998·2 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →