Inventor · disambiguated record
Sukeshwar Kannan
Also filed as: KANNAN SUKESHWAR
12 granted patents·5 pending applications·42 citations·filing 2010–2024
86Inventor score
Top patents by PatentIndex Score
17 records- 0195US11256029B2Photonics packaging method and deviceLIGHTMATTER INC·Filed 2019·Granted Feb 22, 2022·15 cites·11 claims
- 0289US9401312B1TSV redundancy scheme and architecture using decoder/encoderGLOBALFOUNDRIES INC·Filed 2015·Granted Jul 26, 2016·16 cites·19 claims
- 0374US10083958B2Deep trench metal-insulator-metal capacitorsGLOBALFOUNDRIES INC·Filed 2016·Granted Sep 25, 2018·2 cites·19 claims
- 0472US12306434B2Photonic wafer communication systems and related packagesLIGHTMATTER INC·Filed 2024·Granted May 20, 2025·0 cites·19 claims
- 0570US8742777B2Method and system for testing an electric circuitKIM BRUCE C·Filed 2010·Granted Jun 3, 2014·4 cites·18 claims
- 0667US10636776B2Methods of manufacturing RF filtersGLOBALFOUNDRIES INC·Filed 2018·Granted Apr 28, 2020·2 cites·12 claims
- 0767US9716487B1Latency compensation network using timing slack sensorsGLOBALFOUNDRIES INC·Filed 2016·Granted Jul 25, 2017·2 cites·20 claims
- 0864US11947164B2Photonic wafer communication systems and related packagesLIGHTMATTER INC·Filed 2021·Granted Apr 2, 2024·0 cites·20 claims
- 0959US10069490B2Method, apparatus and system for voltage compensation in a semiconductor waferGLOBALFOUNDRIES INC·Filed 2016·Granted Sep 4, 2018·1 cites·18 claims
- 1057US2025141178A1Device and method to control warpage and thermal dissipation in an optical engineAVAGO TECH INT SALES PTE LID·Filed 2023·Application pending·0 cites
- 1156US2025062258A1Method for assembling eic to pic to build an optical engineAVAGO TECH INT SALES PTE LID·Filed 2023·Application pending·0 cites
- 1242US10775429B2Testing monolithic three dimensional integrated circuitsMARVELL INT LTD·Filed 2017·Granted Sep 15, 2020·0 cites·20 claims
- 1342US9460975B2DFT structure for TSVs in 3D ICs while maintaining functional purposeGLOBALFOUNDRIES INC·Filed 2015·Granted Oct 4, 2016·0 cites·20 claims
- 1440US10236263B1Methods and structures for mitigating ESD during wafer bondingGLOBALFOUNDRIES INC·Filed 2017·Granted Mar 19, 2019·0 cites·14 claims
- 1539US2012306096A1Method and model of carbon nanotube based through silicon vias (tsv) for rf applicationsKIM BRUCE·Filed 2012·Application pending·0 cites
- 1633US2016322265A1Method and apparatus for detection of failures in under-fill layers in integrated circuit assembliesGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
- 1733US2016293579A1Integration structures for high current applicationsGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →