Inventor · disambiguated record
Susmita Karmakar
Also filed as: KARMAKAR SUSMITA
11 granted patents·1 pending application·39 citations·filing 2003–2021
85Inventor score
Files withSPIN MEMORY INC6INTEGRATED SILICON SOLUTION CAYMAN INC3SILICON STORAGE TECH INC1SPIN TRANSFER TECH INC1VISPUTE HEMANT1
Top patents by PatentIndex Score
12 records- 0190US10699761B2Word line decoder memory architectureSPIN MEMORY INC·Filed 2018·Granted Jun 30, 2020·9 cites·9 claims
- 0279US7116088B2High voltage shunt regulator for flash memorySILICON STORAGE TECH INC·Filed 2003·Granted Oct 3, 2006·26 cites·8 claims
- 0370US11119910B2Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segmentsSPIN MEMORY INC·Filed 2019·Granted Sep 14, 2021·2 cites·15 claims
- 0463US11586553B2Error cache system with coarse and fine segments for power optimizationINTEGRATED SILICON SOLUTION CAYMAN INC·Filed 2021·Granted Feb 21, 2023·0 cites·20 claims
- 0563US10930332B2Memory array with individually trimmable sense amplifiersSPIN MEMORY INC·Filed 2019·Granted Feb 23, 2021·1 cites·18 claims
- 0661US10360962B1Memory array with individually trimmable sense amplifiersSPIN TRANSFER TECH INC·Filed 2017·Granted Jul 23, 2019·1 cites·15 claims
- 0758US11580014B2Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segmentsINTEGRATED SILICON SOLUTION CAYMAN INC·Filed 2021·Granted Feb 14, 2023·0 cites·20 claims
- 0855US11423965B2Word line decoder memory architectureINTEGRATED SILICON SOLUTION CAYMAN INC·Filed 2020·Granted Aug 23, 2022·0 cites·12 claims
- 0955US11119936B2Error cache system with coarse and fine segments for power optimizationSPIN MEMORY INC·Filed 2019·Granted Sep 14, 2021·0 cites·20 claims
- 1049US11048633B2Determining an inactive memory bank during an idle memory cycle to prevent error cache overflowSPIN MEMORY INC·Filed 2019·Granted Jun 29, 2021·0 cites·20 claims
- 1145US10803949B2Master slave level shift latch for word line decoder memory architectureSPIN MEMORY INC·Filed 2019·Granted Oct 13, 2020·0 cites·22 claims
- 1233US2007216453A1Power-on reset signal generation circuit and methodVISPUTE HEMANT·Filed 2007·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Susmita Karmakar files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →