Inventor · disambiguated record
Sudarshan Kumar
Also filed as: KUMAR SUDARSHAN
32 granted patents·4 pending applications·303 citations·filing 1988–2023
97Inventor score
Top patents by PatentIndex Score
36 records- 0179US6707318B2Low power entry latch to interface static logic with dynamic logicINTEL CORP·Filed 2002·Granted Mar 16, 2004·22 cites·15 claims
- 0276US6351151B2Method and apparatus for reducing soft errors in dynamic circuitsINTEL CORP·Filed 2001·Granted Feb 26, 2002·16 cites·10 claims
- 0374US6952118B2Gate-clocked domino circuits with reduced leakage currentINTEL CORP·Filed 2002·Granted Oct 4, 2005·17 cites·25 claims
- 0469US6820106B1Method and apparatus for improving the performance of a floating point multiplier accumulatorINTEL CORP·Filed 2000·Granted Nov 16, 2004·15 cites·23 claims
- 0566US6631093B2Low power precharge scheme for memory bit linesINTEL CORP·Filed 2001·Granted Oct 7, 2003·16 cites·24 claims
- 0663US6629194B2Method and apparatus for low power memory bit line prechargeINTEL CORP·Filed 2001·Granted Sep 30, 2003·11 cites·17 claims
- 0762US6833735B2Single stage pulsed domino circuit for driving cascaded skewed static logic circuitsINTEL CORP·Filed 2002·Granted Dec 21, 2004·11 cites·14 claims
- 0860US5661675APositive feedback circuit for fast domino logicINTEL CORP·Filed 1995·Granted Aug 26, 1997·43 cites·14 claims
- 0955US6292029B1Method and apparatus for reducing soft errors in dynamic circuitsINTEL CORP·Filed 1999·Granted Sep 18, 2001·11 cites·4 claims
- 1053US4905180AMOS adder with minimum pass gates in carry lineINTEL CORP·Filed 1988·Granted Feb 27, 1990·19 cites·12 claims
- 1148US6124737ALow power clock buffer having a reduced, clocked, pull-down transistorINTEL CORP·Filed 1999·Granted Sep 26, 2000·9 cites·18 claims
- 1247US7685451B2Method and apparatus to limit current-change induced voltage changes in a microcircuitINTEL CORP·Filed 2002·Granted Mar 23, 2010·1 cites·37 claims
- 1347US2022012304A1Fast matrix multiplicationKUMAR SUDARSHAN·Filed 2021·Application pending·0 cites
- 1446US5581497ACarry skip adder with enhanced grouping schemeINTEL CORP·Filed 1994·Granted Dec 3, 1996·16 cites·21 claims
- 1546US5136539AAdder with intermediate carry circuitINTEL CORP·Filed 1988·Granted Aug 4, 1992·14 cites·13 claims
- 1645US2025022491A1System for saving leakage power in static random access memory (sram) using light sleep modeDXCORR DESIGN INC·Filed 2023·Application pending·0 cites
- 1742US6593776B2Method and apparatus for low power domino decodingINTEL CORP·Filed 2001·Granted Jul 15, 2003·3 cites·21 claims
- 1842US5579254AFast static CMOS adderINTEL CORP·Filed 1995·Granted Nov 26, 1996·13 cites·12 claims
- 1941US11915745B2Low standby leakage implementation for static random access memoryDXCORR DESIGN INC·Filed 2021·Granted Feb 27, 2024·0 cites·13 claims
- 2041US5471414AFast static CMOS adderINTEL CORP·Filed 1993·Granted Nov 28, 1995·11 cites·26 claims
- 2140US6628539B2Multi-entry register cellINTEL CORP·Filed 2001·Granted Sep 30, 2003·0 cites·24 claims
- 2239US6127850ALow power clock buffer with shared, clocked transistorINTEL CORP·Filed 1999·Granted Oct 3, 2000·5 cites·18 claims
- 2339US5900744AMethod and apparatus for providing a high speed tristate bufferINTEL CORP·Filed 1996·Granted May 4, 1999·7 cites·15 claims
- 2438US6369616B1Low power clock buffer with shared, precharge transistorINTEL CORP·Filed 2000·Granted Apr 9, 2002·1 cites·15 claims
- 2538US6058403ABroken stack priority encoderINTEL CORP·Filed 1998·Granted May 2, 2000·10 cites·28 claims
- 2635US2022013154A1Low Power Content Addressable MemoryKUMAR SUDARSHAN·Filed 2021·Application pending·0 cites
- 2733US6266757B1High speed four-to-two carry save adderINTEL CORP·Filed 1998·Granted Jul 24, 2001·5 cites·14 claims
- 2833US5889693ACMOS sum select incrementorINTEL CORP·Filed 1997·Granted Mar 30, 1999·6 cites·20 claims
- 2933US2012057135A1Low power and low cost projection systemKUMAR SUDARSHAN·Filed 2010·Application pending·0 cites
- 3032US6111435ALow power multiplexer with shared, clocked transistorINTEL CORP·Filed 1999·Granted Aug 29, 2000·2 cites·18 claims
- 3132US5944777AMethod and apparatus for generating carries in an adder circuitINTEL CORP·Filed 1997·Granted Aug 31, 1999·4 cites·3 claims
- 3231US6205463B1Fast 2-input 32-bit domino adderINTEL CORP·Filed 1997·Granted Mar 20, 2001·6 cites·18 claims
- 3331US6023767AMethod for verifying hold time in integrated circuit designINTEL CORP·Filed 1997·Granted Feb 8, 2000·5 cites·11 claims
- 3430US6341099B1Reducing power consumption in a data storage deviceINTEL CORP·Filed 2000·Granted Jan 22, 2002·0 cites·15 claims
- 3527US11017858B1Low power content addressable memoryKUMAR SUDARSHAN·Filed 2016·Granted May 25, 2021·0 cites·16 claims
- 3624US5608741AFast parity generator using complement pass-transistor logicINTEL CORP·Filed 1993·Granted Mar 4, 1997·4 cites·23 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →