Inventor · disambiguated record
Subhash R. Nariani
Also filed as: NARIANI SUBHASH · NARIANI SUBHASH R · NARIANI SUBHASH REWACHAND
23 granted patents·1 pending application·676 citations·filing 1990–2012
97Inventor score
Top patents by PatentIndex Score
24 records- 0196US8106516B1Wafer-level chip scale packageLACAP EFREN M·Filed 2010·Granted Jan 31, 2012·26 cites·38 claims
- 0290US5587332AMethod of making flash memory cellVLSI TECHNOLOGY INC·Filed 1992·Granted Dec 24, 1996·72 cites·43 claims
- 0389US5120679AAnti-fuse structures and methods for making sameVLSI TECHNOLOGY INC·Filed 1991·Granted Jun 9, 1992·116 cites·16 claims
- 0488US5493146AAnti-fuse structure for reducing contamination of the anti-fuse materialVLSI TECHNOLOGY INC·Filed 1994·Granted Feb 20, 1996·77 cites·22 claims
- 0583US5290734AMethod for making anti-fuse structuresVLSI TECHNOLOGY INC·Filed 1991·Granted Mar 1, 1994·78 cites·15 claims
- 0672US5470775AMethod of forming a polysilicon-on-silicide capacitorVLSI TECHNOLOGY INC·Filed 1993·Granted Nov 28, 1995·32 cites·16 claims
- 0772US5057897ACharge neutralization using silicon-enriched oxide layerVLSI TECHNOLOGY INC·Filed 1990·Granted Oct 15, 1991·49 cites·8 claims
- 0864US5328865AMethod for making cusp-free anti-fuse structuresVLSI TECHNOLOGY INC·Filed 1993·Granted Jul 12, 1994·35 cites·11 claims
- 0962US5128279ACharge neutralization using silicon-enriched oxide layerVLSI TECHNOLOGY INC·Filed 1991·Granted Jul 7, 1992·30 cites·5 claims
- 1059US5573970AMethod for reducing contamination of anti-fuse material in an anti-fuse structureVLSI TECHNOLOGY INC·Filed 1995·Granted Nov 12, 1996·19 cites·19 claims
- 1159US5548224AMethod and apparatus for wafer level prediction of thin oxide reliabilityVLSI TECHNOLOGY INC·Filed 1995·Granted Aug 20, 1996·21 cites·20 claims
- 1258US5638006AMethod and apparatus for wafer level prediction of thin oxide reliability using differentially sized gate-like antennaeVLSI TECHNOLOGY INC·Filed 1995·Granted Jun 10, 1997·20 cites·20 claims
- 1357US5290727AMethod for suppressing charge loss in EEPROMs/EPROMS and instabilities in SRAM load resistorsVLSI TECHNOLOGY INC·Filed 1992·Granted Mar 1, 1994·26 cites·17 claims
- 1455US8710664B2Wafer-level chip scale packageLACAP EFREN M·Filed 2012·Granted Apr 29, 2014·0 cites·10 claims
- 1548US5218511AInter-silicide capacitorVLSI TECHNOLOGY INC·Filed 1992·Granted Jun 8, 1993·11 cites·20 claims
- 1647US5763937ADevice reliability of MOS devices using silicon rich plasma oxide filmsVLSI TECHNOLOGY INC·Filed 1994·Granted Jun 9, 1998·16 cites·12 claims
- 1746US5602056AMethod for forming reliable MOS devices using silicon rich plasma oxide filmVLSI TECHNOLOGY INC·Filed 1995·Granted Feb 11, 1997·12 cites·13 claims
- 1845US6015732ADual gate oxide process with increased reliabilityVLSI TECHNOLOGY INC·Filed 1996·Granted Jan 18, 2000·10 cites·14 claims
- 1942US2005045697A1Wafer-level chip scale packageFiled 2003·Application pending·0 cites
- 2041USRE36893EAnti-fuse structure for reducing contamination of the anti-fuse materialVLSI TECHNOLOGY INC·Filed 1997·Granted Oct 3, 2000·7 cites·22 claims
- 2140US5198381AMethod of making an E2 PROM cell with improved tunneling properties having two implant stagesVLSI TECHNOLOGY INC·Filed 1991·Granted Mar 30, 1993·6 cites·14 claims
- 2237US5374833AStructure for suppression of field inversion caused by charge build-up in the dielectricVLSI TECHNOLOGY INC·Filed 1991·Granted Dec 20, 1994·7 cites·17 claims
- 2337US5371393AEEPROM cell with improved tunneling propertiesVLSI TECHNOLOGY INC·Filed 1994·Granted Dec 6, 1994·4 cites·7 claims
- 2431US5492865AMethod of making structure for suppression of field inversion caused by charge build-up in the dielectricVLSI TECHNOLOGY INC·Filed 1994·Granted Feb 20, 1996·2 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →