Inventor · disambiguated record
Suresh Venkata Pothukuchi
Also filed as: POTHUKUCHI SURESH · POTHUKUCHI SURESH V · POTHUKUCHI SURESH VENKATA
7 granted patents·9 pending applications·11 citations·filing 2010–2025
76Inventor score
Top patents by PatentIndex Score
16 records- 0189US8786066B2Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming sameGUZEK JOHN S·Filed 2010·Granted Jul 22, 2014·11 cites·36 claims
- 0283US2025372590A1Electro-optical memory circuit packageCELESTIAL AI INC·Filed 2025·Application pending·0 cites
- 0383US2025370183A1Electro-optical memory circuit packageCELESTIAL AI INC·Filed 2025·Application pending·0 cites
- 0480US2025372587A1Electro-optical memory circuit packageCELESTIAL AI INC·Filed 2025·Application pending·0 cites
- 0579US12494403B2Preserving access to optical components on a wafer package with sacrificial dieCELESTIAL AI INC·Filed 2025·Granted Dec 9, 2025·0 cites·22 claims
- 0678US12493155B2Preserving access to optical components on a wafer package with sacrificial capCELESTIAL AI INC·Filed 2025·Granted Dec 9, 2025·0 cites·27 claims
- 0774US2025038163A1Optical multichip package with multiple system-on-chip diesINTEL CORP·Filed 2024·Application pending·0 cites
- 0865US12148744B2Optical multichip package with multiple system-on-chip diesINTEL CORP·Filed 2020·Granted Nov 19, 2024·0 cites·17 claims
- 0962US11830863B2Dual-sided co-packaged optics for high bandwidth networking applicationsINTEL CORP·Filed 2021·Granted Nov 28, 2023·0 cites·19 claims
- 1061US11217573B2Dual-sided co-packaged optics for high bandwidth networking applicationsINTEL CORP·Filed 2020·Granted Jan 4, 2022·0 cites·25 claims
- 1153US9406618B2Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming sameINTEL CORP·Filed 2014·Granted Aug 2, 2016·0 cites·32 claims
- 1253US2025208204A1Double-sided integrated circuit package apparatus and related methodsINTEL CORP·Filed 2023·Application pending·0 cites
- 1352US2025006651A1Slit fiducials for integrated circuit device alignmentINTEL CORP·Filed 2023·Application pending·0 cites
- 1450US2014327149A1Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming sameGUZEK JOHN S·Filed 2014·Application pending·0 cites
- 1545US2021210478A1Packaging solutions for high bandwidth networking applicationsINTEL CORP·Filed 2021·Application pending·0 cites
- 1640US2023401130A1Fpga based platform for post-silicon validation of chipletsINTEL CORP·Filed 2022·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →