Inventor · disambiguated record
Sushobhit Singh
Also filed as: SINGH SUSHOBHIT
9 granted patents·114 citations·filing 2012–2022
86Inventor score
Technology areasG06F
Top patents by PatentIndex Score
9 records- 0194US8769455B1Methods, systems, and articles of manufacture for synchronous hierarchical implementation of electronic circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2012·Granted Jul 1, 2014·27 cites·35 claims
- 0292US8572532B1Common path pessimism removal for hierarchical timing analysisSINGH SUSHOBHIT·Filed 2012·Granted Oct 29, 2013·42 cites·22 claims
- 0390US8977995B1Timing budgeting of nested partitions for hierarchical integrated circuit designsARORA SUMIT·Filed 2012·Granted Mar 10, 2015·36 cites·19 claims
- 0484US11455450B1System and method for performing sign-off timing analysis of electronic circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Sep 27, 2022·2 cites·13 claims
- 0577US10783300B1Systems and methods for extracting hierarchical path exception timing modelsCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Sep 22, 2020·4 cites·16 claims
- 0670US10733346B1Systems and methods for arc-based debugging in an electronic designCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Aug 4, 2020·1 cites·20 claims
- 0770US9053270B1Methods, systems, and articles of manufacture for synchronous hierarchical implementation of electronic circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Jun 9, 2015·2 cites·20 claims
- 0856US12332304B1System and method for automatic fault detection in an electronic designCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Jun 17, 2025·0 cites·20 claims
- 0953US11347915B1System and method for objective probing and generation of timing constraints associated with an electronic circuit designCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted May 31, 2022·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →