Inventor · disambiguated record
Sunil Sudhakaran
Also filed as: SUDHAKARAN SUNIL · SUDHAKARAN SUNIL RAO
19 granted patents·1 pending application·158 citations·filing 2012–2023
92Inventor score
Top patents by PatentIndex Score
20 records- 0195US8638241B28b/9b decoding for reducing crosstalk on a high speed parallel busSUDHAKARAN SUNIL·Filed 2012·Granted Jan 28, 2014·80 cites·20 claims
- 0294US10979176B1Codebook to reduce error growth arising from channel errorsNVIDIA CORP·Filed 2020·Granted Apr 13, 2021·8 cites·19 claims
- 0393US11695601B2On-chip virtual oscilloscope using high-speed receiver sampler readbackNVIDIA CORP·Filed 2021·Granted Jul 4, 2023·12 cites·20 claims
- 0493US10491238B2Maximum transition avoidance (MTA) encodingNVIDIA CORP·Filed 2018·Granted Nov 26, 2019·20 cites·16 claims
- 0591US9693311B2Method of providing user with battery power notification in mobile device and mobile device thereforSAMSUNG ELECTRONICS CO LTD·Filed 2015·Granted Jun 27, 2017·28 cites·20 claims
- 0688US12135607B2Hardware-efficient PAM-3 encoder and decoderNVIDIA CORP·Filed 2023·Granted Nov 5, 2024·1 cites·27 claims
- 0782US10623200B2Bus-invert coding with restricted hamming distance for multi-byte interfacesNVIDIA CORP·Filed 2018·Granted Apr 14, 2020·3 cites·11 claims
- 0877US10594337B2Maximum transition avoidance (MTA) encodingNVIDIA CORP·Filed 2019·Granted Mar 17, 2020·3 cites·21 claims
- 0973US12197281B2Hardware-efficient PAM-3 encoder and decoderNVIDIA CORP·Filed 2023·Granted Jan 14, 2025·0 cites·28 claims
- 1061US10032710B2Via pattern to reduce crosstalk between differential signal pairsNVIDIA CORP·Filed 2015·Granted Jul 24, 2018·1 cites·22 claims
- 1161US8614634B28b/9b encoding for reducing crosstalk on a high speed parallel busSUDHAKARAN SUNIL·Filed 2012·Granted Dec 24, 2013·1 cites·20 claims
- 1260US12132590B2Hardware-efficient PAM-3 encoder and decoderNVIDIA CORP·Filed 2022·Granted Oct 29, 2024·0 cites·16 claims
- 1360US11573854B2Techniques for data scrambling on a memory interfaceNVIDIA CORP·Filed 2021·Granted Feb 7, 2023·0 cites·20 claims
- 1460US10685925B2Resistance and capacitance balancing systems and methodsNVIDIA CORP·Filed 2018·Granted Jun 16, 2020·1 cites·17 claims
- 1551US12347508B2Error detection pin encoding scheme to avoid maximum transitions and further improve signal integrity on high speed graphic memory interfacesNVIDIA CORP·Filed 2022·Granted Jul 1, 2025·0 cites·25 claims
- 1650US11439010B2Via pattern for framebuffer interfacesNVIDIA CORP·Filed 2020·Granted Sep 6, 2022·0 cites·30 claims
- 1743US2021043329A1Method and device for determining cause of trend in vital sign dataSAMSUNG ELECTRONICS CO LTD·Filed 2019·Application pending·0 cites
- 1842US10074411B2Mode-changeable dual data rate random access memory driver with asymmetric offset and memory interface incorporating the sameNVIDIA CORP·Filed 2014·Granted Sep 11, 2018·0 cites·20 claims
- 1940US10901017B2Systematic methodology to remove reflections from I/O measurementsNVIDIA CORP·Filed 2017·Granted Jan 26, 2021·0 cites·14 claims
- 2039US10600730B2Cross talk reduction differential cross over routing systems and methodsNVIDIA CORP·Filed 2018·Granted Mar 24, 2020·0 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →