Via pattern for framebuffer interfaces

Abstract

This disclosure provides a multi-layered printed circuit board (PC) that has signal array region. The signal array region has a width and circumscribes a power core region and has signal vias connected to respective signal ball pads, and ground vias connected to respective ground ball pads within the signal array region that have an associated ball pad pitch. The PCB also has an inner current power layer. The signal and ground vias are arranged on the component layer in a pattern and extend into the inner current layer. The pattern forms current power paths across the width of the signal array region, such that the current power paths have a width that is at least about 50% as wide as the ball pad pitch.

What is claimed is: 
     
       1. A multi-layered printed circuit board (PCB), comprising:
 a component layer having a signal array region located thereon, the signal array region having a width and circumscribing a power core region, the signal array region having signal vias connected to a respective signal ball pad and ground vias connected to a respective ground ball pad within the signal array region, the signal and ground ball pads forming a ball pad pitch, wherein a portion of the signal vias form first microstrips and another portion of the signal vias form second microstrips and a length of the first microstrips is different than a length of the second microstrips; and 
 an inner current power layer, wherein the signal and ground vias are arranged on the component layer in a pattern and extend into the inner current power layer, the pattern forming current power paths across the width of the signal array region, such that the current power paths have a width that is at least 50% as wide as the ball pad pitch. 
 
     
     
       2. The multi-layered PCB of  claim 1 , wherein current power paths have a width that is at least 75% as wide as the ball pitch of the outer layer. 
     
     
       3. The multi-layered PCB of  claim 1 , wherein the signal vias are located along signal diagonal paths within the signal array region and the ground vias are located along ground diagonal paths within the width of the signal array region. 
     
     
       4. The multi-layered PCB of  claim 1 , wherein the ball pad pitch ranges from 0.65 mm to 1.0 mm. 
     
     
       5. The multi-layered PCB of  claim 1 , wherein each signal via has a ground via located on opposing sides thereof. 
     
     
       6. The multi-layered PCB of  claim 1 , wherein the signal array region is a framebuffer signal array region. 
     
     
       7. The multi-layered PCB of  claim 1 , wherein the length of the first microstrips is greater than the length of the second microstrips. 
     
     
       8. The multi-layered PCB of  claim 3 , wherein the signal diagonal paths intersect, and the ground diagonal path intersect to form respective “X” patterns of the signal vias and the ground vias within the signal array region. 
     
     
       9. The multi-layered PCB of  claim 5 , wherein a ratio of ground vias to signal vias is 4:1. 
     
     
       10. The multi-layered PCB of  claim 7 , wherein the first microstrips have a length of greater than 500 microns and the second microstrips have a length of 500 microns or less. 
     
     
       11. The multi-layered PCB of  claim 10 , wherein the signal and ground vias are arranged in alternating rows and columns of signal vias and ground vias within the signal array, and the first and second microstrips form an altering pattern along the rows and columns. 
     
     
       12. An electronics device graphics card, comprising:
 a printed circuitry board comprising:
 a component layer having a signal array region located thereon, the signal array region having a width and circumscribing a power core region, the signal array region having signal vias connected to a respective signal ball pad and ground vias connected to a respective ground ball pad within the signal array region, the signal and ground ball pads forming a ball pad pitch, wherein a portion of the signal vias form first microstrips and another portion of the signal vias form second microstrips and a length of the first microstrips is different than a length of the second microstrips; and 
 an inner current power layer, wherein the signal and ground vias are arranged on the component layer in a pattern and extend into the inner current layer, the pattern forming current power paths across the width of the signal array region, such that the current power paths have a width that is at least 50% as wide as the ball pad pitch; 
 
 a graphics processor unit (GPU) located on and electrically connected to the printed circuit board; and 
 memory located on the printed circuit board and electrically connected to the GPU. 
 
     
     
       13. The electronics device graphics card of  claim 12 , wherein the GPU has an integrated crosstalk noise value of 5.5 mV or less. 
     
     
       14. The electronics device graphics card of  claim 12 , wherein current power paths have a width that is at least 75% as wide as the ball pitch of the outer layer. 
     
     
       15. The electronics device graphics card of  claim 12 , wherein the signal vias are located along signal diagonal paths within the signal array region and the ground vias are located along ground diagonal paths within the width of the signal array region. 
     
     
       16. The electronics device graphics card of  claim 12 , wherein the ball pad pitch ranges from 0.65 mm to 1.0 mm. 
     
     
       17. The electronics device graphics card of  claim 12 , wherein each signal via has a ground via located on opposing sides thereof such that a ratio of ground vias to signal vias is 4:1. 
     
     
       18. The electronics device graphics card of  claim 12 , wherein the signal array region is separated from the power core region by a differential signal region. 
     
     
       19. The electronics device graphics card of  claim 12 , wherein the length of the first microstrips is greater than the length of the second microstrips. 
     
     
       20. The electronics device graphics card of  claim 15 , wherein the signal diagonal paths intersect, and the ground diagonal path intersect to form respective “X” patterns of the signal vias and the ground vias within the signal array region. 
     
     
       21. The electronics device graphics card of  claim 19 , wherein the first microstrips have a length of greater than 500 microns and the second microstrips have a length of 500 microns or less. 
     
     
       22. The electronics device graphics card of  claim 21 , wherein the signal and ground vias are arranged in alternating rows and columns of signal vias and ground vias within the signal array, and the first and second microstrips form an altering pattern along the rows and columns. 
     
     
       23. A method of fabricating a printed circuit board (PCB), comprising:
 forming signal and ground vias on a component layer of the PCB in a signal array region and in a signal via pattern and a ground via pattern, the signal array region having a width and circumscribing a power core region, wherein the signal and ground vias are arranged on the component layer in a pattern and extend into the inner current layer, the pattern forming current power paths across the width of the signal array region, such that the current power paths have a width that is at least 50% as wide as the ball pad pitch, and wherein a portion of the signal vias form first microstrips and another portion of the signal vias form second microstrips and a length of the first microstrips is different than a length of the second microstrips; 
 forming signal ball pads and ground ball pads on the outer layer and within the signal array region, the signal and ground ball pads forming a ball pad pitch; and 
 electrically connecting each signal via to at least one signal ball pad and each ground via to at least one ground ball pad with a conductive trace. 
 
     
     
       24. The method of  claim 23 , wherein current power paths have a width that is at least 75% as wide as the ball pitch of the outer layer. 
     
     
       25. The method of  claim 23 , wherein the signal vias are located along signal diagonal paths within the signal array region and the ground vias are located along ground diagonal paths within the width of the signal array region. 
     
     
       26. The method of  claim 23 , wherein the ball pad pitch ranges from 0.65 mm to 1.0 mm and the PCB has a ratio of ground vias to signal vias of 4:1. 
     
     
       27. The multi-layered PCB of  claim 1 , wherein the signal array region is separated from the power core region by a differential signal region. 
     
     
       28. The method of  claim 23 , wherein the length of the first microstrips is greater than the length of the second microstrip. 
     
     
       29. The method of  claim 25 , wherein the signal diagonal paths intersect, and the ground diagonal path intersect to form respective “X” patterns of the signal vias and the ground vias within the signal array region. 
     
     
       30. The method of  claim 28 , wherein the first microstrips have a length of greater than 500 microns and the second microstrips have a length of 500 microns or less.