Inventor · disambiguated record
Su-Jen Sung
Also filed as: SUNG SU-JEN
29 granted patents·11 pending applications·52 citations·filing 2006–2025
95Inventor score
Files withTAIWAN SEMICONDUCTOR MFG CO LTD29TAIWAN SEMICONDUCTOR MFG4CHEN MEI-LING3UNITED MICROELECTRONICS CORP3CHEN WEI CHIH1
Top patents by PatentIndex Score
40 records- 0192US12094930B2Integrated circuit structure and method for forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Sep 17, 2024·2 cites·20 claims
- 0290US10163794B2Capping layer for improved deposition selectivityTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Dec 25, 2018·6 cites·20 claims
- 0388US10510666B2Interconnect structure and method of forming sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Dec 17, 2019·4 cites·20 claims
- 0487US9852905B2Systems and methods for uniform gas flow in a deposition chamberTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Dec 26, 2017·8 cites·20 claims
- 0585US9041216B2Interconnect structure and method of forming the sameTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted May 26, 2015·6 cites·20 claims
- 0685US2025343090A1HIGHLY PROTECTIVE WAFER EDGE SIDEWALLl PROTECTION LAYERTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 0784US11502035B2Interconnect structure and method of forming sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Nov 15, 2022·2 cites·20 claims
- 0884US11282742B2Semiconductor device with multi-layer etch stop structure and method for forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Mar 22, 2022·2 cites·20 claims
- 0982US12198979B2Semiconductor device with multi-layer etch stop structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Jan 14, 2025·0 cites·20 claims
- 1082US9129965B2Semiconductor devices and methods of manufacture thereofTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Sep 8, 2015·4 cites·20 claims
- 1181US12255095B2Semiconductor structure and manufacturing method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Mar 18, 2025·0 cites·20 claims
- 1281US2025112102A1HIGHLY PROTECTIVE WAFER EDGE SIDEWALLl PROTECTION LAYERTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 1380US11923304B2Electro-migration barrier for interconnectTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Mar 5, 2024·0 cites·20 claims
- 1479US12046557B2Interconnect structure and method of forming sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Jul 23, 2024·0 cites·20 claims
- 1579US2024387252A1Semiconductor structure and manufacturing method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 1678US9530728B2Semiconductor devices and methods of manufacture thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Dec 27, 2016·2 cites·20 claims
- 1777US9396990B2Capping layer for improved deposition selectivityTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted Jul 19, 2016·3 cites·18 claims
- 1875US9490209B2Electro-migration barrier for Cu interconnectTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted Nov 8, 2016·2 cites·20 claims
- 1975US2024379541A1Nitrogen Plasma Treatment For Improving Interface Between Etch Stop Layer And Copper InterconnectTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 2074US12211766B2Highly protective wafer edge sidewall protection layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Jan 28, 2025·0 cites·20 claims
- 2174US11848231B2Method for forming semiconductor device with multi-layer etch stop structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Dec 19, 2023·0 cites·20 claims
- 2274US8084357B2Method for manufacturing a dual damascene opening comprising a trench opening and a via openingCHEN WEI-CHIH·Filed 2007·Granted Dec 27, 2011·5 cites·8 claims
- 2374US2024379517A1Wafer bonding incorporating thermal conductive pathsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 2473US11515255B2Electro-migration barrier for interconnectTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Nov 29, 2022·0 cites·20 claims
- 2573US2024387630A1Integrated circuit structure and method for forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 2672US12159830B2Nitrogen plasma treatment for improving interface between etch stop layer and copper interconnectTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Dec 3, 2024·0 cites·20 claims
- 2771US11670546B2Semiconductor structure and manufacturing method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Jun 6, 2023·0 cites·20 claims
- 2870US7947565B2Forming method of porous low-k layer and interconnect processUNITED MICROELECTRONICS CORP·Filed 2007·Granted May 24, 2011·4 cites·17 claims
- 2969US8350246B2Structure of porous low-k layer and interconnect structureUNITED MICROELECTRONICS CORP·Filed 2011·Granted Jan 8, 2013·2 cites·25 claims
- 3063US2023154837A1Wafer Bonding Incorporating Thermal Conductive PathsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Application pending·0 cites
- 3162US10867920B2Electro-migration barrier for Cu interconnectTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Dec 15, 2020·0 cites·20 claims
- 3259US11264328B2Capping layer for improved deposition selectivityTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Mar 1, 2022·0 cites·20 claims
- 3357US10163795B2Electro-migration barrier for Cu interconnectTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Dec 25, 2018·0 cites·20 claims
- 3454US2014272135A1Deposition injection maskingTAIWAN SEMICONDUCTOR MFG·Filed 2013·Application pending·0 cites
- 3551US11532548B2Nitrogen plasma treatment for improving interface between etch stop layer and copper interconnectTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Dec 20, 2022·0 cites·20 claims
- 3651US2009275211A1Fabrication method of porous low-k dielectric filmCHEN MEI-LING·Filed 2009·Application pending·0 cites
- 3750US9355894B2Interconnect structure and method of forming the sameTAIWAN SEMICONDUCTOR MFG·Filed 2015·Granted May 31, 2016·0 cites·20 claims
- 3844US2007173070A1Porous low-k dielectric film and fabrication method thereofCHEN MEI-LING·Filed 2006·Application pending·0 cites
- 3944US2008166498A1Method of curing porous low-k layerUNITED MICROELECTRONICS CORP·Filed 2007·Application pending·0 cites
- 4043US8092861B2Method of fabricating an ultra dielectric constant (K) dielectric layerCHEN MEI-LING·Filed 2007·Granted Jan 10, 2012·0 cites·12 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →