Inventor · disambiguated record
Taranjit Singh Kukal
Also filed as: KUKAL TARANJIT · KUKAL TARANJIT SINGH
35 granted patents·515 citations·filing 2006–2021
98Inventor score
Technology areasG06F
Top patents by PatentIndex Score
35 records- 0197US9223915B1Method, system, and computer program product for checking, verifying, or testing a multi-fabric electronic design spanning across multiple design fabricsCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Dec 29, 2015·39 cites·20 claims
- 0295US10289793B1System and method to generate schematics from layout-fabrics with a common cross-fabric modelCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted May 14, 2019·16 cites·20 claims
- 0395US9881120B1Method, system, and computer program product for implementing a multi-fabric mixed-signal design spanning across multiple design fabrics with electrical and thermal analysis awarenessCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Jan 30, 2018·18 cites·20 claims
- 0495US9881119B1Methods, systems, and computer program product for constructing a simulation schematic of an electronic design across multiple design fabricsCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Jan 30, 2018·19 cites·21 claims
- 0593US10558780B1Methods, systems, and computer program product for implementing schematic driven extracted views for an electronic designCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Feb 11, 2020·20 cites·20 claims
- 0693US10285276B1Method and apparatus to drive layout of arbitrary EM-coil through parametrized cellCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted May 7, 2019·17 cites·19 claims
- 0793US9449130B1Methods, systems, and articles of manufacture for back annotating and visualizing parasitic models of electronic designsCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Sep 20, 2016·10 cites·20 claims
- 0893US9286421B1Methods, systems, and articles of manufacture for back annotating and visualizing parasitic models of electronic designsCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Mar 15, 2016·16 cites·20 claims
- 0993US9280621B1Methods, systems, and articles of manufacture for analyzing a multi-fabric electronic design and displaying analysis results for the multi-fabric electronic design spanning and displaying simulation results across multiple design fabricsCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Mar 8, 2016·12 cites·20 claims
- 1093US8286110B1System and method for adapting electrical integrity analysis to parametrically integrated environmentKUKAL TARANJIT SINGH·Filed 2010·Granted Oct 9, 2012·26 cites·24 claims
- 1192US9361415B1Method, system, and computer program product for implementing a multi-fabric electronic design spanning across multiple design fabricsCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Jun 7, 2016·10 cites·20 claims
- 1292US9348960B1Method, system, and computer program product for probing or netlisting a multi-fabric electronic design spanning across multiple design fabricsCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted May 24, 2016·10 cites·20 claims
- 1392US8656329B1System and method for implementing power integrity topology adapted for parametrically integrated environmentKUKAL TARANJIT SINGH·Filed 2010·Granted Feb 18, 2014·29 cites·23 claims
- 1491US9934354B1Methods, systems, and computer program product for implementing a layout-driven, multi-fabric schematic designCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Apr 3, 2018·15 cites·20 claims
- 1591US7490309B1Method and system for automatically optimizing physical implementation of an electronic circuit responsive to simulation analysisCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Feb 10, 2009·31 cites·24 claims
- 1690US10997332B1System and method for computing electrical over-stress of devices associated with an electronic designCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted May 4, 2021·10 cites·20 claims
- 1790US8521483B1Method and apparatus for concurrent design of modules across different design entry tools targeted to single simulationKUKAL TARANJIT·Filed 2010·Granted Aug 27, 2013·18 cites·27 claims
- 1890US8452582B1System and method for adapting behavioral models to fluctuations in parametrically integrated environmentAL-HAWARI FERAS·Filed 2010·Granted May 28, 2013·19 cites·30 claims
- 1989US10528688B1System and method for schematic-driven generation of input/output modelsCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Jan 7, 2020·9 cites·18 claims
- 2089US8316342B1Method and apparatus for concurrent design of modules across different design entry tools targeted to a single layoutKUKAL TARANJIT·Filed 2010·Granted Nov 20, 2012·24 cites·28 claims
- 2188US9928318B1System and method for simulating channelsCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Mar 27, 2018·8 cites·20 claims
- 2287US10467370B1Methods, systems, and computer program product for implementing a net as a transmission line model in a schematic driven extracted view for an electronic designCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Nov 5, 2019·7 cites·20 claims
- 2387US8566767B1System and method for parametric intercoupling of static and dynamic analyses for synergistic integration in electronic design automationKUKAL TARANJIT·Filed 2011·Granted Oct 22, 2013·25 cites·29 claims
- 2486US10678978B1Methods, systems, and computer program product for binding and back annotating an electronic design with a schematic driven extracted viewCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Jun 9, 2020·5 cites·20 claims
- 2584US10726188B1Method, system, and computer program product for performing channel analyses for an electronic circuit design including a parallel interfaceCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Jul 28, 2020·4 cites·20 claims
- 2684US9454634B1Methods, systems, and computer program product for an integrated circuit package design estimatorCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Sep 27, 2016·10 cites·20 claims
- 2783US11354477B1System and method for performance estimation for electronic designs using subcircuit matching and data-reuseCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Jun 7, 2022·2 cites·20 claims
- 2883US9798848B1Method, system, and computer program product for performing channel analyses for an electronic circuit design including a parallel interfaceCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Oct 24, 2017·7 cites·20 claims
- 2983US8898039B1Physical topology-driven logical design flowKUKAL TARANJIT SINGH·Filed 2009·Granted Nov 25, 2014·16 cites·27 claims
- 3082US10643020B1System and method to estimate a number of layers needed for routing a multi-die packageCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted May 5, 2020·8 cites·20 claims
- 3181US8645894B1Configuration and analysis of design variants of multi-domain circuitsKUKAL TARANJIT SINGH·Filed 2008·Granted Feb 4, 2014·16 cites·9 claims
- 3281US8145458B1Method and system for automatic stress analysis of analog components in digital electronic circuitKUKAL TARANJIT SINGH·Filed 2007·Granted Mar 27, 2012·18 cites·20 claims
- 3380US8732651B1Logical design flow with structural compatability verificationKUKAL TARANJIT SINGH·Filed 2009·Granted May 20, 2014·13 cites·23 claims
- 3478US10783307B1System and method for power-grid aware simulation of an IC-package schematicCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Sep 22, 2020·2 cites·20 claims
- 3577US9785141B2Method, system, and computer program product for schematic driven, unified thermal and electromagnetic interference compliance analyses for electronic circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Oct 10, 2017·6 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →