Inventor · disambiguated record
Tanuj Kumar
Also filed as: KUMAR TANUJ
5 granted patents·2 pending applications·0 citations·filing 2019–2024
59Inventor score
Top patents by PatentIndex Score
7 records- 0166US2025069678A1Built-in self test circuit for segmented static random access memory (sram) array input/outputST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 0263US12437825B2At-speed transition fault testing for a multi-port and multi-clock memoryST MICROELECTRONICS INT NV·Filed 2023·Granted Oct 7, 2025·0 cites·40 claims
- 0362US12170120B2Built-in self test circuit for segmented static random access memory (SRAM) array input/outputST MICROELECTRONICS INT NV·Filed 2023·Granted Dec 17, 2024·0 cites·38 claims
- 0456US12353341B2Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selectionST MICROELECTRONICS INT NV·Filed 2023·Granted Jul 8, 2025·0 cites·19 claims
- 0547US2024431123A1Thread-Based TransistorsTUFTS COLLEGE·Filed 2022·Application pending·0 cites
- 0645US11025252B2Circuit for detection of single bit upsets in generation of internal clock for memoryST MICROELECTRONICS INT NV·Filed 2019·Granted Jun 1, 2021·0 cites·25 claims
- 0736US11393532B2Circuit and method for at speed detection of a word line fault condition in a memory circuitST MICROELECTRONICS INT NV·Filed 2020·Granted Jul 19, 2022·0 cites·25 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →