Inventor · disambiguated record
Tad Kwasniewski
Also filed as: KWASNIEWSKI TAD
28 granted patents·4 pending applications·524 citations·filing 2002–2011
97Inventor score
Top patents by PatentIndex Score
32 records- 0196US7633322B1Digital loop circuit for programmable logic deviceALTERA CORP·Filed 2007·Granted Dec 15, 2009·48 cites·45 claims
- 0295US7580497B2Clock data recovery loop with separate proportional pathALTERA CORP·Filed 2005·Granted Aug 25, 2009·35 cites·9 claims
- 0395US7385429B1Charge pump with reduced current mismatchALTERA CORP·Filed 2005·Granted Jun 10, 2008·26 cites·13 claims
- 0494US7224191B1Differential signal detector methods and apparatusALTERA CORP·Filed 2006·Granted May 29, 2007·34 cites·7 claims
- 0593US7693691B1Systems and methods for simulating link performanceALTERA CORP·Filed 2006·Granted Apr 6, 2010·36 cites·33 claims
- 0691US7940098B1Fractional delay-locked loopsALTERA CORP·Filed 2010·Granted May 10, 2011·13 cites·20 claims
- 0791US7656323B2Apparatus for all-digital serializer-de-serializer and associated methodsALTERA CORP·Filed 2008·Granted Feb 2, 2010·25 cites·26 claims
- 0890US7675332B1Fractional delay-locked loopsALTERA CORP·Filed 2007·Granted Mar 9, 2010·23 cites·30 claims
- 0989US7143312B1Alignment of recovered clock with data signalALTERA CORP·Filed 2003·Granted Nov 28, 2006·42 cites·19 claims
- 1086US7902888B1Charge pump with reduced current mismatchALTERA CORP·Filed 2008·Granted Mar 8, 2011·12 cites·23 claims
- 1183US6956407B2Pre-emphasis circuitry and methodsALTERA CORP·Filed 2003·Granted Oct 18, 2005·37 cites·26 claims
- 1281US7598779B1Dual-mode LVDS/CML transmitter methods and apparatusALTERA CORP·Filed 2004·Granted Oct 6, 2009·33 cites·24 claims
- 1379US8217693B2Charge pump with reduced current mismatchMEI HAITAO·Filed 2011·Granted Jul 10, 2012·5 cites·19 claims
- 1478US7196557B1Multitap fractional baud period pre-emphasis for data transmissionALTERA CORP·Filed 2004·Granted Mar 27, 2007·23 cites·28 claims
- 1578US6970020B1Half-rate linear quardrature phase detector for clock recoveryALTERA CORP·Filed 2003·Granted Nov 29, 2005·17 cites·8 claims
- 1677US7528635B2Multitap fractional baud period pre-emphasis for data transmissionALTERA CORP·Filed 2007·Granted May 5, 2009·6 cites·18 claims
- 1775US7697603B1Methods and apparatus for equalization in high-speed backplane data communicationALTERA CORP·Filed 2004·Granted Apr 13, 2010·21 cites·29 claims
- 1875US7474167B1Capacitance switch circuitry for digitally controlled oscillatorsALTERA CORP·Filed 2006·Granted Jan 6, 2009·6 cites·25 claims
- 1975US7061334B1Apparatus and methods for wide tuning-range ring oscillatorsALTERA CORP·Filed 2004·Granted Jun 13, 2006·17 cites·17 claims
- 2072US7848402B1Phase-adjusted pre-emphasis and equalization for data communicationALTERA CORP·Filed 2005·Granted Dec 7, 2010·5 cites·21 claims
- 2172US7486752B1Alignment of clock signal with data signalALTERA CORP·Filed 2003·Granted Feb 3, 2009·17 cites·30 claims
- 2271US7157944B1Differential signal detector methods and apparatusALTERA CORP·Filed 2004·Granted Jan 2, 2007·12 cites·13 claims
- 2370US7388443B2Apparatus and method for wide tuning-range ring oscillatorsALTERA CORP·Filed 2006·Granted Jun 17, 2008·5 cites·38 claims
- 2468US8014480B1Zero-delay serial communications circuitry for serial interconnectsALTERA CORP·Filed 2007·Granted Sep 6, 2011·6 cites·18 claims
- 2567US8098588B1Blind adaptive decision feedback equalizer for high-speed serial communicationsBERNDT CHARLES E·Filed 2007·Granted Jan 17, 2012·7 cites·19 claims
- 2665US7239849B2Adaptive communication methods and apparatusALTERA CORP·Filed 2003·Granted Jul 3, 2007·11 cites·42 claims
- 2755US7414484B2Voltage controlled oscillator circuitry and methodsALTERA CORP·Filed 2005·Granted Aug 19, 2008·2 cites·18 claims
- 2847US2010027607A1Apparatus for time-domain pre-emphasis and time-domain equalization and associated methodsKWASNIEWSKI TAD·Filed 2008·Application pending·0 cites
- 2940US2009302887A1Apparatus for power consumption reduction in programmable logic devices and associated methodsKWASNIEWSKI TAD·Filed 2008·Application pending·0 cites
- 3039US7843275B1Frequency synthesizer circuitry employing delay lineALTERA CORP·Filed 2007·Granted Nov 30, 2010·0 cites·14 claims
- 3136US2005160327A1Input stage threshold adjustment for high speed data communicationsALTERA CORP·Filed 2004·Application pending·0 cites
- 3232US2003141919A1Active peaking using differential pairs of transistorsFiled 2002·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →