Half-rate linear quardrature phase detector for clock recovery

Abstract

A half-rate linear phase detector is particularly well-suited to clock data recovery in a serial data interface. The phase detector uses a quadrature clock to process different portions of the incoming data with different phases of the clock. The resulting component signals can be combined to provide the expected UP and DOWN phase detector output control signals. The phase detector output signals are balanced and of uniform width, minimizing oscillator control signal ripple in the clock data recovery circuit, while the linearity of the phase detector makes its output predictable.

1. A phase detector for providing an UP control signal and a DOWN control signal in a high-speed loop circuit based on relative alignment between a full-rate data signal and a clock signal derived by said loop circuit, said phase detector comprising:
 circuitry for deriving a half-rate quadrature clock from said derived clock signal; 
 circuitry for comparing a first quadrature phase of said half-rate quadrature clock with even pulses of said data signal to derive a first portion of said UP control signal; 
 circuitry for comparing a second quadrature phase of said half-rate quadrature clock with odd pulses of said data signal to derive a second portion of said UP control signal; 
 circuitry for comparing a third quadrature phase of said half-rate quadrature clock with even pulses of said data signal to derive a first portion of said DOWN control signal; 
 circuitry for comparing a fourth quadrature phase of said half-rate quadrature clock with odd pulses of said data signal to derive a second portion of said DOWN control signal; 
 circuitry for combining said first and second portions of said UP control signal into a single UP control signal; and 
 circuitry for combining said first and second portions of said DOWN control signal into a single DOWN control signal. 
 
   
   
     2. The phase detector of  claim 1  wherein each said respective circuitry for comparing comprises a clocked exclusive-OR circuit, clocked by the respective quadrature phase being compared by said respective circuitry for comparing. 
   
   
     3. The phase detector of  claim 1  wherein each respective circuitry for comparing comprises a respective OR gate. 
   
   
     4. A method for providing an UP control signal and a DOWN control signal in a phase detector of a loop circuit based on relative alignment between a full-rate data signal and a clock signal derived by said loop circuit, said method comprising:
 deriving a half-rate quadrature clock from said derived clock signal; 
 comparing a first quadrature phase of said half-rate quadrature clock with even pulses of said data signal to derive a first portion of said UP control signal; 
 comparing a second quadrature phase of said half-rate quadrature clock with odd pulses of said data signal to derive a second portion of said UP control signal; 
 comparing a third quadrature phase of said half-rate quadrature clock with even pulses of said data signal to derive a first portion of said DOWN control signal; 
 comparing a fourth quadrature phase of said half-rate quadrature clock with odd pulses of said data signal to derive a second portion of said DOWN control signal; 
 combining said first and second portions of said UP control signal into a single UP control signal; and 
 combining said first and second portions of said DOWN control signal into a single DOWN control signal. 
 
   
   
     5. A method for detecting phase error in a loop circuit based on relative alignment between a full-rate data signal and a clock signal derived by said loop circuit, said method comprising:
 deriving a half-rate quadrature clock from said derived clock signal; 
 comparing first and second phases of said half-rate quadrature clock with respective portions of said full-rate data signal to derive respective partial UP phase error signals; 
 comparing third and fourth phases of said half-rate quadrature clock with respective portions of said full-rate data signal to derive respective partial DOWN phase error signals; and 
 combining said respective partial phase error signals to derive at least one signal representing said phase error. 
 
   
   
     6. The method of  claim 5  wherein said combining comprises:
 combining a first component of said respective partial phase error signals into a single UP control signal; and 
 combining a second portion component of said respective partial phase error signals into a single DOWN control signal. 
 
   
   
     7. The method of  claim 5  wherein:
 said comparing first and second phases of said half-rate quadrature clock with respective portions of said full-rate data signal to derive respective partial UP phase error signals comprises:
 comparing a first quadrature phase of said half-rate quadrature clock with even pulses of said data signal to derive a first component of an UP control signal, and 
 comparing a second quadrature phase of said half-rate quadrature clock with odd pulses of said data signal to derive a second component of said UP control signal; and 
 said comparing third and fourth phases of said half-rate quadrature clock with respective portions of said full-rate data signal to derive respective partial DOWN phase error signals comprises: 
 comparing a third quadrature phase of said half-rate quadrature clock with even pulses of said data signal to derive a first component of a DOWN control signal; and 
 comparing a fourth quadrature phase of said half-rate quadrature clock with odd pulses of said data signal to derive a second component of said DOWN control signal. 
 
 
   
   
     8. The method of  claim 7  wherein said combining comprises:
 combining said first and second components of said UP control signal into a single UP control signal; and 
 combining said first and second components of said DOWN control signal into a single DOWN control signal.