Inventor · disambiguated record
Terence Cheung
Also filed as: CHEUNG TERENCE
7 granted patents·1 pending application·23 citations·filing 2007–2020
78Inventor score
Technology areasH10W
Top patents by PatentIndex Score
8 records- 0180US9209106B2Thermal management circuit board for stacked semiconductor chip deviceSHI XIAO LING·Filed 2012·Granted Dec 8, 2015·10 cites·28 claims
- 0276US8314474B2Under bump metallization for on-die capacitorMCLELLAN NEIL·Filed 2008·Granted Nov 20, 2012·8 cites·30 claims
- 0367US8012874B2Semiconductor chip substrate with multi-capacitor footprintATI TECHNOLOGIES ULC·Filed 2007·Granted Sep 6, 2011·5 cites·13 claims
- 0457US11437307B2Device comprising first solder interconnects aligned in a first direction and second solder interconnects aligned in a second directionQUALCOMM INC·Filed 2020·Granted Sep 6, 2022·0 cites·14 claims
- 0555US11764076B2Semi-embedded trace structure with partially buried tracesQUALCOMM INC·Filed 2020·Granted Sep 19, 2023·0 cites·20 claims
- 0652US10916494B2Device comprising first solder interconnects aligned in a first direction and second solder interconnects aligned in a second directionQUALCOMM INC·Filed 2019·Granted Feb 9, 2021·0 cites·12 claims
- 0751US11552023B2Passive component embedded in an embedded trace substrate (ETS)QUALCOMM INC·Filed 2020·Granted Jan 10, 2023·0 cites·16 claims
- 0843US2009032941A1Under Bump Routing Layer Method and ApparatusMCLELLAN NEIL·Filed 2007·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →