Inventor · disambiguated record
Thomas Ludwig
Also filed as: LUDWIG THOMAS · LUDWIG THOMAS RICHARD
24 granted patents·3 pending applications·897 citations·filing 1987–2010
96Inventor score
Top patents by PatentIndex Score
27 records- 0198US7456471B2Field effect transistor with raised source/drain fin strapsIBM·Filed 2006·Granted Nov 25, 2008·85 cites·20 claims
- 0296US7309626B2Quasi self-aligned source/drain FinFET processIBM·Filed 2005·Granted Dec 18, 2007·139 cites·11 claims
- 0396US6909147B2Multi-height FinFETSIBM·Filed 2003·Granted Jun 21, 2005·171 cites·35 claims
- 0494US7315994B2Method and device for automated layer generation for double-gate FinFET designsIBM·Filed 2004·Granted Jan 1, 2008·199 cites·8 claims
- 0592US7851283B2Field effect transistor with raised source/drain fin strapsIBM·Filed 2008·Granted Dec 14, 2010·16 cites·20 claims
- 0692US7323374B2Dense chevron finFET and method of manufacturing sameIBM·Filed 2005·Granted Jan 29, 2008·22 cites·21 claims
- 0787US8418110B2Using port obscurity factors to improve routingKEINERT JOACHIM·Filed 2010·Granted Apr 9, 2013·12 cites·10 claims
- 0882US4815113AMethod for digital slope control of output signals of power amplifiers in semiconductor chipsIBM·Filed 1987·Granted Mar 21, 1989·30 cites·11 claims
- 0980US5016087AIntegrated circuit packageIBM·Filed 1990·Granted May 14, 1991·62 cites·30 claims
- 1077US5744996ACMOS integrated semiconductor circuitIBM·Filed 1993·Granted Apr 28, 1998·48 cites·9 claims
- 1176US5680063ABi-directional voltage translatorMOTOROLA INC·Filed 1996·Granted Oct 21, 1997·31 cites·20 claims
- 1271US8429584B2Method, electronic design automation tool, computer program product, and data processing program for creating a layout for design representation of an electronic circuit and corresponding port for an electronic circuitKEINERT JOACHIM·Filed 2010·Granted Apr 23, 2013·3 cites·15 claims
- 1371US8020120B2Layout quality gauge for integrated circuit designIBM·Filed 2007·Granted Sep 13, 2011·7 cites·18 claims
- 1469US7962877B2Port assignment in hierarchical designs by abstracting macro logicIBM·Filed 2008·Granted Jun 14, 2011·4 cites·20 claims
- 1567US8762919B2Circuit macro placement using macro aspect ratio based on portsKEINERT JOACHIM·Filed 2010·Granted Jun 24, 2014·2 cites·18 claims
- 1660US8495551B2Shaping ports in integrated circuit designKEINERT JOACHIM·Filed 2010·Granted Jul 23, 2013·1 cites·12 claims
- 1758US5162264AIntegrated circuit packageIBM·Filed 1991·Granted Nov 10, 1992·24 cites·30 claims
- 1850US7990158B2Measurement arrangement for determining the characteristic line parameters by measuring scattering parametersIBM·Filed 2008·Granted Aug 2, 2011·1 cites·16 claims
- 1948US8423947B2Gridded glyph geometric objects (L3GO) design methodLAVIN MARK A·Filed 2008·Granted Apr 16, 2013·0 cites·17 claims
- 2048US2008042202A1QUASI SELF-ALIGNED SOURCE/DRAIN FinFET PROCESSIBM·Filed 2007·Application pending·0 cites
- 2147US5306866AModule for electronic packageIBM·Filed 1992·Granted Apr 26, 1994·19 cites·11 claims
- 2244US8963294B2Dense chevron finFET and method of manufacturing sameBEINTNER JOCHEN·Filed 2007·Granted Feb 24, 2015·0 cites·14 claims
- 2341US2009050975A1Active Silicon Interconnect in Merged Finfet ProcessBRYANT ANDRES·Filed 2007·Application pending·0 cites
- 2440US5928319ACombined binary/decimal adder unitIBM·Filed 1997·Granted Jul 27, 1999·13 cites·12 claims
- 2533US5944772ACombined adder and logic unitIBM·Filed 1997·Granted Aug 31, 1999·6 cites·18 claims
- 2632US4967104ACircuit for increasing the output impedance of an amplifierIBM·Filed 1989·Granted Oct 30, 1990·2 cites·6 claims
- 2732US2008136423A1Measurement Arrangement for Determining the Characteristic line Parameters by Measuring Scattering ParametersLUDWIG THOMAS·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →