QUASI SELF-ALIGNED SOURCE/DRAIN FinFET PROCESS

Abstract

A method of forming a semiconductor structure including a plurality of finFFET devices in which crossing masks are employed in providing a rectangular patterns to define relatively thin Fins along with a chemical oxide removal (COR) process is provided. The present method further includes a step of merging adjacent Fins by the use of a selective silicon-containing material. The present invention also relates to the resultant semiconductor structure that is formed utilizing the method of the present invention.

1 . A semiconductor structure comprising: 
 a plurality of FinFET devices located on a surface of a semiconductor substrate, each of said FinFET including an elevated semiconducting layer that has wider end portions relative to its middle portion, a gate region that crosses said middle portion, and source/drain regions within said wider end portions; and    a Si-containing material located between said elevated semiconducting layer which joins each elevated semiconducting layer.    
     
     
         2 . The semiconductor structure of  claim 1  wherein said elevated semiconducting layer is a top semiconducting layer of an SOI substrate, said SOI substrate including a buried insulating layer that is patterned or unpatterned and an unpatterned bottom semiconducting layer.  
     
     
         3 . The semiconductor structure of  claim 2  wherein said elevated semiconducting layer is a Si-containing semiconductor and said buried insulating layer is an oxide.  
     
     
         4 . The semiconductor structure of  claim 1  wherein each gate region comprises a gate dielectric and a gate electrode.  
     
     
         5 . The semiconductor structure of  claim 1  further comprising a gate spacer located around each gate region.  
     
     
         6 . The semiconductor structure of  claim 1  wherein said elevated semiconducting layer is an upper surface layer of a bulk semiconductor substrate.  
     
     
         7 . The semiconductor structure of  claim 1  wherein said Si-containing material comprises one of single crystalline Si, SiGe or SiGeC.  
     
     
         8 . The semiconductor structure of  claim 1  wherein said end portions of the elevated semiconducting layer are substantially square.