Inventor · disambiguated record
Thomas C. Mcdonald
Also filed as: MCDONALD THOMAS · MCDONALD THOMAS C · MCDONALD THOMAS COLVIN · MCDONALD THOMAS G
43 granted patents·6 pending applications·549 citations·filing 1983–2021
98Inventor score
Top patents by PatentIndex Score
49 records- 0194USD283204SGarden hose water meterMCDONALD THOMAS C·Filed 1983·Granted Apr 1, 1986·38 cites·1 claims
- 0293US7707397B2Variable group associativity branch target address cache delivering multiple target addresses per cache lineVIA TECH INC·Filed 2005·Granted Apr 27, 2010·34 cites·74 claims
- 0390US6886093B2Speculative hybrid branch direction predictorIP FIRST LLC·Filed 2001·Granted Apr 26, 2005·56 cites·41 claims
- 0489US11275686B1Adjustable write policies controlled by feature control registersCENTAUR TECH INC·Filed 2020·Granted Mar 15, 2022·2 cites·20 claims
- 0588US6823444B1Apparatus and method for selectively accessing disparate instruction buffer stages based on branch target address cache hit and instruction stage wrapIP FIRST LLC·Filed 2001·Granted Nov 23, 2004·47 cites·11 claims
- 0687US6895498B2Apparatus and method for target address replacement in speculative branch target address cacheIP FIRST LLC·Filed 2001·Granted May 17, 2005·45 cites·2 claims
- 0785US7117347B2Processor including fallback branch prediction mechanism for far jump and far call instructionsIP FIRST LLC·Filed 2002·Granted Oct 3, 2006·42 cites·15 claims
- 0880US7165169B2Speculative branch target address cache with selective override by secondary predictor based on branch instruction typeIP FIRST LLC·Filed 2001·Granted Jan 16, 2007·28 cites·69 claims
- 0978US7237098B2Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequenceIP FIRST LLC·Filed 2003·Granted Jun 26, 2007·22 cites·48 claims
- 1077US7203824B2Apparatus and method for handling BTAC branches that wrap across instruction cache linesIP FIRST LLC·Filed 2001·Granted Apr 10, 2007·24 cites·27 claims
- 1177US6314514B1Method and apparatus for correcting an internal call/return stack in a microprocessor that speculatively executes call and return instructionsIP FIRST LLC·Filed 1999·Granted Nov 6, 2001·76 cites·38 claims
- 1273US7234045B2Apparatus and method for handling BTAC branches that wrap across instruction cache linesIP FIRST LLC·Filed 2005·Granted Jun 19, 2007·6 cites·20 claims
- 1371US8832418B2Efficient branch target address cache entry replacementMCDONALD THOMAS C·Filed 2009·Granted Sep 9, 2014·5 cites·30 claims
- 1471US7140196B2Chilled beverage dispenser with cradle evaporatorGRINDMASTER CORP·Filed 2005·Granted Nov 28, 2006·6 cites·18 claims
- 1569US7398377B2Apparatus and method for target address replacement in speculative branch target address cacheIP FIRST LLC·Filed 2004·Granted Jul 8, 2008·11 cites·28 claims
- 1669US7134005B2Microprocessor that detects erroneous speculative prediction of branch instruction opcode byteIP FIRST LLC·Filed 2001·Granted Nov 7, 2006·14 cites·15 claims
- 1766US7200740B2Apparatus and method for speculatively performing a return instruction in a microprocessorIP FIRST LLC·Filed 2001·Granted Apr 3, 2007·11 cites·36 claims
- 1866US7165168B2Microprocessor with branch target address cache update queueIP FIRST LLC·Filed 2003·Granted Jan 16, 2007·12 cites·30 claims
- 1964US7631172B2Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequenceIP FIRST LLC·Filed 2006·Granted Dec 8, 2009·2 cites·29 claims
- 2063US8281110B2Out-of-order microprocessor with separate branch information circular queue table tagged by branch instructions in reorder buffer to reduce unnecessary space in bufferMCDONALD THOMAS C·Filed 2009·Granted Oct 2, 2012·2 cites·26 claims
- 2163US7162619B2Apparatus and method for densely packing a branch instruction predicted by a branch target address cache and associated target instructions into a byte-wide instruction bufferIP FIRST LLC·Filed 2001·Granted Jan 9, 2007·9 cites·52 claims
- 2260US11113067B1Speculative branch pattern updateCENTAUR TECH INC·Filed 2020·Granted Sep 7, 2021·0 cites·18 claims
- 2360US7178010B2Method and apparatus for correcting an internal call/return stack in a microprocessor that detects from multiple pipeline stages incorrect speculative update of the call/return stackIP FIRST LLC·Filed 2003·Granted Feb 13, 2007·7 cites·75 claims
- 2458US11783050B2Spectre fixes with predictor mode tagCENTAUR TECH INC·Filed 2020·Granted Oct 10, 2023·0 cites·16 claims
- 2558US11567776B2Branch density detection for prefetcherCENTAUR TECH INC·Filed 2020·Granted Jan 31, 2023·0 cites·20 claims
- 2657US11461103B2Dual branch execute and table update with single portCENTAUR TECH INC·Filed 2020·Granted Oct 4, 2022·0 cites·18 claims
- 2757US7152154B2Apparatus and method for invalidation of redundant branch target address cache entriesIP FIRST LLC·Filed 2003·Granted Dec 19, 2006·6 cites·23 claims
- 2857US5831459AMethod and system for adjusting a clock signal within electronic circuitryIBM·Filed 1997·Granted Nov 3, 1998·33 cites·3 claims
- 2956US11360774B2Dual branch formatCENTAUR TECH INC·Filed 2020·Granted Jun 14, 2022·0 cites·20 claims
- 3056US11334491B1Side cache array for greater fetch bandwidthCENTAUR TECH INC·Filed 2020·Granted May 17, 2022·0 cites·18 claims
- 3156US8838938B2Prefix accumulation for efficient processing of instructions with multiple prefix bytesMCDONALD THOMAS C·Filed 2009·Granted Sep 16, 2014·0 cites·23 claims
- 3256US8612727B2Apparatus and method for marking start and end bytes of instructions in a stream of instruction bytes in a microprocessor having an instruction set architecture in which instructions may include a length-modifying prefixMCDONALD THOMAS C·Filed 2009·Granted Dec 17, 2013·0 cites·23 claims
- 3356US8473726B2Bad branch prediction detection, marking, and accumulation for faster instruction stream processingMCDONALD THOMAS C·Filed 2009·Granted Jun 25, 2013·0 cites·26 claims
- 3456US8438367B2Instruction extraction through prefix accumulationMCDONALD THOMAS C·Filed 2009·Granted May 7, 2013·0 cites·23 claims
- 3556US8335910B2Early release of cache data with start/end marks when instructions are only partially presentMCDONALD THOMAS C·Filed 2009·Granted Dec 18, 2012·0 cites·24 claims
- 3655US11614944B2Small branch predictor escapeCENTAUR TECH INC·Filed 2020·Granted Mar 28, 2023·0 cites·18 claims
- 3755US7159098B2Selecting next instruction line buffer stage based on current instruction line boundary wraparound and branch target in buffer indicatorIP FIRST LLC·Filed 2004·Granted Jan 2, 2007·3 cites·41 claims
- 3854US11500643B2Spectre fixes with indirect valid tableCENTAUR TECH INC·Filed 2020·Granted Nov 15, 2022·0 cites·20 claims
- 3953US7185186B2Apparatus and method for resolving deadlock fetch conditions involving branch target address cacheIP FIRST LLC·Filed 2003·Granted Feb 27, 2007·4 cites·19 claims
- 4050US8533434B2Apparatus for efficiently determining instruction length instruction within a stream of x86 instruction bytesDUNCAN JOHN L·Filed 2009·Granted Sep 10, 2013·0 cites·27 claims
- 4150US7159097B2Apparatus and method for buffering instructions and late-generated related information using history of previous load/shiftsIP FIRST LLC·Filed 2003·Granted Jan 2, 2007·2 cites·41 claims
- 4250US7143269B2Apparatus and method for killing an instruction after loading the instruction into an instruction queue in a pipelined microprocessorIP FIRST LLC·Filed 2003·Granted Nov 28, 2006·2 cites·54 claims
- 4349US2005132175A1Speculative hybrid branch direction predictorIP FIRST LLC·Filed 2004·Application pending·0 cites
- 4448US11995447B2Quick predictor override and update by a BTACCENTAUR TECH INC·Filed 2020·Granted May 28, 2024·0 cites·20 claims
- 4546US2006130399A1Pole baseMCDONALD THOMAS G·Filed 2005·Application pending·0 cites
- 4645US2022355707A1Vehicle with Enhanced Entertainment and Storage OptionsMCDONALD THOMAS·Filed 2021·Application pending·0 cites
- 4743US2005144427A1Processor including branch prediction mechanism for far jump and far call instructionsIP FIRST LLC·Filed 2002·Application pending·0 cites
- 4842US2002194461A1Speculative branch target address cacheIP FIRST LLC·Filed 2001·Application pending·0 cites
- 4942US2002194462A1Apparatus and method for selecting one of multiple target addresses stored in a speculative branch target address cache per instruction cache lineIP FIRST LLC·Filed 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →