Inventor · disambiguated record
Theo J. Powell
Also filed as: POWELL THEO J · POWELL THEO JAY
21 granted patents·2 pending applications·1,022 citations·filing 1983–2006
97Inventor score
Files withTEXAS INSTRUMENTS INC21
Top patents by PatentIndex Score
23 records- 0194US4710931APartitioned scan-testing systemTEXAS INSTRUMENTS INC·Filed 1985·Granted Dec 1, 1987·104 cites·17 claims
- 0293US4701921AModularized scan path for serially tested logic circuitTEXAS INSTRUMENTS INC·Filed 1985·Granted Oct 20, 1987·113 cites·16 claims
- 0393US4698588ATransparent shift register latch for isolating peripheral ports during scan testing of a logic circuitTEXAS INSTRUMENTS INC·Filed 1985·Granted Oct 6, 1987·108 cites·11 claims
- 0491US4710933AParallel/serial scan system for testing logic circuitsTEXAS INSTRUMENTS INC·Filed 1985·Granted Dec 1, 1987·77 cites·15 claims
- 0590US4597080AArchitecture and method for testing VLSI processorsTEXAS INSTRUMENTS INC·Filed 1983·Granted Jun 24, 1986·60 cites·1 claims
- 0688US6801461B2Built-in self-test arrangement for integrated circuit memory devicesTEXAS INSTRUMENTS INC·Filed 2001·Granted Oct 5, 2004·39 cites·42 claims
- 0787US5883843ABuilt-in self-test arrangement for integrated circuit memory devicesTEXAS INSTRUMENTS INC·Filed 1997·Granted Mar 16, 1999·68 cites·6 claims
- 0887US5032783ATest circuit and scan tested logic device with isolated data lines during testingTEXAS INSTRUMENTS INC·Filed 1989·Granted Jul 16, 1991·58 cites·18 claims
- 0981US6014336ATest enable control for built-in self-testTEXAS INSTRUMENTS INC·Filed 1998·Granted Jan 11, 2000·47 cites·55 claims
- 1080US7274581B1Array fault testing approach for TCAMsTEXAS INSTRUMENTS INC·Filed 2006·Granted Sep 25, 2007·13 cites·17 claims
- 1179US5694402ASystem and method for structurally testing integrated circuit devicesTEXAS INSTRUMENTS INC·Filed 1996·Granted Dec 2, 1997·94 cites·20 claims
- 1273US7328388B2Built-in self-test arrangement for integrated circuit memory devicesTEXAS INSTRUMENTS INC·Filed 2006·Granted Feb 5, 2008·4 cites·6 claims
- 1371US5923599AApparatus and method for subarray testing in dynamic random access memories using a built-in-self-test unitTEXAS INSTRUMENTS INC·Filed 1997·Granted Jul 13, 1999·30 cites·12 claims
- 1470US7278078B2Built-in self-test arrangement for integrated circuit memory devicesTEXAS INSTRUMENTS INC·Filed 2004·Granted Oct 2, 2007·12 cites·19 claims
- 1569US6353563B1Built-in self-test arrangement for integrated circuit memory devicesTEXAS INSTRUMENTS INC·Filed 1999·Granted Mar 5, 2002·55 cites·43 claims
- 1669US4870346ADistributed pseudo random sequence control with universal polynomial function generator for LSI/VLSI test systemsTEXAS INSTRUMENTS INC·Filed 1987·Granted Sep 26, 1989·25 cites·22 claims
- 1767US5936900AIntegrated circuit memory device having built-in self test circuit with monitor and tester modesTEXAS INSTRUMENTS INC·Filed 1997·Granted Aug 10, 1999·31 cites·15 claims
- 1864US5875153AInternal/external clock option for built-in self testTEXAS INSTRUMENTS INC·Filed 1998·Granted Feb 23, 1999·43 cites·12 claims
- 1959US5953272AData invert jump instruction test for built-in self-testTEXAS INSTRUMENTS INC·Filed 1998·Granted Sep 14, 1999·18 cites·10 claims
- 2052US5959912AROM embedded mask release number for built-in self-testTEXAS INSTRUMENTS INC·Filed 1998·Granted Sep 28, 1999·13 cites·2 claims
- 2137US5012471AValue-strength based test pattern generator and processTEXAS INSTRUMENTS INC·Filed 1988·Granted Apr 30, 1991·10 cites·4 claims
- 2233US2002071325A1Built-in self-test arrangement for integrated circuit memory devicesFiled 2001·Application pending·0 cites
- 2328US2005144525A1Method to test memories that operate at twice their nominal bandwidthFiled 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →