Built-in self-test arrangement for integrated circuit memory devices

Abstract

An integrated circuit has a built-in self-test (BIST) arrangement ( 60 ). The built-in self-test arrangement includes a read only memory (ROM), ( 140 ) that stores test algorithm instructions. A ROM logic circuit ( 410 ) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register 420 receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.

What is claimed is:  
     
         1 . An integrated circuit having a built-in self-test (BIST) arrangement, the built-in self-test arrangement comprising: 
 a read only memory storing test algorithm instructions;    a logic circuit, interconnected with the read only memory, for receiving an instruction read from the read only memory and producing at an output terminal a group of output signals dependent upon the instruction; and    a BIST register, connected with the output terminal, for receiving and storing the group of output signals from the logic circuit.    
     
     
         2 . The integrated circuit having a built-in self-test arrangement, in accordance with  claim 1 , the built-in self-test arrangement further comprising: 
 a timing generator, interconnected with the BIST register, for receiving the signals stored in the BIST register and for producing row address strobes, column address strobes and a write enable signal.    
     
     
         3 . The integrated circuit hating a built-in self-test arrangement, in accordance with  claim 2 , the built-in self-test arrangement further comprising: 
 a multiplexer having plural groups of input terminals, a group of input control terminals, and a group of output terminals;    a first bus, interconnecting a first group of input terminals of the multiplexer to the BIST register, for conveying the signals stored in the BIST register to the multiplexer; and    a second bus, interconnecting the group of input control terminals of the multiplexer, for transmitting the row address strobes, the column address strobes, and the write enable signal to the multiplexer.    
     
     
         4 . The integrated circuit having a built-in self-test arrangement, in accordance with  claim 2 , the built-in self-test arrangement further comprising: 
 an oscillator for producing a BIST cloak signal;    a BIST program counter, arranged for counting in response to the BIST clock signal;    a third bus, interconnecting a group of input terminals of the BIST program counter to the BIST register, for conveying signals stored in the BIST register to the BIST program counter;    a BIST address decoder, responsive to a count in the BIST program counter, for decoding the count and producing a signal for selecting a row address for the read only memory; and    a fourth bus, interconnecting row address inputs of the read only memory to the BIST address decoder, for conveying the decoded row address from the BIST address decoder to the row address inputs of the read only memory.    
     
     
         5 . The integrated circuit having a built-in self-test arrangement, in accordance with  claim 4 , wherein: 
 the BIST program counter includes: 
 a reset input for receiving a reset signal for setting the BIST program counter to a predetermined initial state;  
 an increment input for receiving an increment the counter signal for incrementing a count state stored in the BIST program counter; and  
 a jump input for receiving a jump signal for causing the state of the BIST program counter to change to a state represented by signals conveyed from the BIST register.  
   
     
     
         6 . An integrated circuit memory array device having a built-in self-test (BIST) arrangement, the memory device comprising: 
 an address buffer for receiving and storing a sequence of addresses;    a built-in self-test detector, responsive to input signals, for controlling operation of the device alternatively in either a normal mode or a self-test mode;    address range registers, arranged for receiving and storing start and end addresses, for a self-test operation of the memory array while the device is operating in the self-test mode; and    a self-test address counter, interconnected with the address range registers and the address buffer, for applying to the address buffer a sequence of addresses commencing with the start address and stopping at the end address.