Inventor · disambiguated record
Thomas W. Williams
Also filed as: WILLIAMS THOMAS · WILLIAMS THOMAS W · WILLIAMS THOMAS WALTER
29 granted patents·1 pending application·1,114 citations·filing 1976–2010
98Inventor score
Top patents by PatentIndex Score
30 records- 0197US6950974B1Efficient compression and application of deterministic patterns in a logic BIST architectureSYNOPSYS INC·Filed 2001·Granted Sep 27, 2005·92 cites·30 claims
- 0296US7900105B2Dynamically reconfigurable shared scan-in test architectureSYNOPSYS INC·Filed 2010·Granted Mar 1, 2011·15 cites·35 claims
- 0395US4063080AMethod of propagation delay testing a level sensitive array logic systemIBM·Filed 1976·Granted Dec 13, 1977·48 cites·25 claims
- 0494US6993694B1Deterministic bist architecture including MISR filterSYNOPSYS INC·Filed 2002·Granted Jan 31, 2006·75 cites·12 claims
- 0593US6807646B1System and method for time slicing deterministic patterns for reseeding in logic built-in self-testSYNOPSYS INC·Filed 2002·Granted Oct 19, 2004·61 cites·26 claims
- 0693US4503386AChip partitioning aid (CPA)-A structure for test pattern generation for large logic networksIBM·Filed 1982·Granted Mar 5, 1985·80 cites·19 claims
- 0792US6385750B1Method and system for controlling test data volume in deterministic test pattern generationSYNOPSYS INC·Filed 1999·Granted May 7, 2002·97 cites·30 claims
- 0892US4293919ALevel sensitive scan design (LSSD) systemIBM·Filed 1979·Granted Oct 6, 1981·61 cites·3 claims
- 0990US7418640B2Dynamically reconfigurable shared scan-in test architectureSYNOPSYS INC·Filed 2004·Granted Aug 26, 2008·28 cites·7 claims
- 1090US4051352ALevel sensitive embedded array logic systemIBM·Filed 1976·Granted Sep 27, 1977·41 cites·16 claims
- 1189US6766501B1System and method for high-level test planning for layoutSYNOPSYS INC·Filed 2002·Granted Jul 20, 2004·34 cites·26 claims
- 1289US4074851AMethod of level sensitive testing a functional logic system with embedded arrayIBM·Filed 1976·Granted Feb 21, 1978·35 cites·26 claims
- 1388US4509008AMethod of concurrently testing each of a plurality of interconnected integrated circuit chipsIBM·Filed 1984·Granted Apr 2, 1985·56 cites·1 claims
- 1487US6990619B1System and method for automatically retargeting test vectors between different tester typesSYNOPSYS INC·Filed 2001·Granted Jan 24, 2006·38 cites·29 claims
- 1586US7774663B2Dynamically reconfigurable shared scan-in test architectureSYNOPSYS INC·Filed 2009·Granted Aug 10, 2010·8 cites·7 claims
- 1685US7596733B2Dynamically reconfigurable shared scan-in test architectureSYNOPSYS INC·Filed 2008·Granted Sep 29, 2009·8 cites·7 claims
- 1784US7836367B2Dynamically reconfigurable shared scan-in test architectureSYNOPSYS INC·Filed 2009·Granted Nov 16, 2010·7 cites·56 claims
- 1883US7814444B2Scan compression circuit and method of design thereforSYNOPSYS INC·Filed 2007·Granted Oct 12, 2010·16 cites·17 claims
- 1980US6615380B1Dynamic scan chains and test pattern generation methodologies thereforSYNOPSYS INC·Filed 1999·Granted Sep 2, 2003·91 cites·21 claims
- 2080US6434733B1System and method for high-level test planning for layoutSYNOPSYS INC·Filed 1999·Granted Aug 13, 2002·39 cites·26 claims
- 2179US6405355B1Method for placement-based scan-in and scan-out ports selectionSYNOPSYS INC·Filed 1999·Granted Jun 11, 2002·43 cites·22 claims
- 2277US7669098B2Method and apparatus for limiting power dissipation in testSYNOPSYS INC·Filed 2006·Granted Feb 23, 2010·8 cites·20 claims
- 2375US4071902AReduced overhead for clock testing in a level system scan design (LSSD) systemIBM·Filed 1976·Granted Jan 31, 1978·23 cites·14 claims
- 2471US7836368B2Dynamically reconfigurable shared scan-in test architectureSYNOPSYS INC·Filed 2009·Granted Nov 16, 2010·3 cites·28 claims
- 2565US7743299B2Dynamically reconfigurable shared scan-in test architectureSYNOPSYS INC·Filed 2008·Granted Jun 22, 2010·2 cites·5 claims
- 2662US6631344B1Method and system for performing deterministic analysis and speculative analysis for more efficient automatic test pattern generationSYNOPSYS INC·Filed 1999·Granted Oct 7, 2003·41 cites·13 claims
- 2761US4277699ALatch circuit operable as a D-type edge triggerIBM·Filed 1979·Granted Jul 7, 1981·24 cites·4 claims
- 2858US6453437B1Method and system for performing transition fault simulation along long circuit paths for high-quality automatic test pattern generationSYNOPSYS INC·Filed 1999·Granted Sep 17, 2002·32 cites·15 claims
- 2944US4726023ADetermination of testability of combined logic end memory by ignoring memoryIBM·Filed 1986·Granted Feb 16, 1988·8 cites·6 claims
- 3032US2002093356A1Intelligent test vector formatting to reduce test vector size and allow encryption thereof for integrated circuit testingFiled 2000·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →