Inventor · disambiguated record
Timothy O. Dickson
Also filed as: DICKSON TIMOTHY · DICKSON TIMOTHY O
21 granted patents·176 citations·filing 2008–2022
94Inventor score
Top patents by PatentIndex Score
21 records- 0197US9699009B1Dual-mode non-return-to-zero (NRZ)/ four-level pulse amplitude modulation (PAM4) receiver with digitally enhanced NRZ sensitivityIBM·Filed 2016·Granted Jul 4, 2017·79 cites·16 claims
- 0295US9942028B1Serial transmitter with feed forward equalizer and timing calibrationIBM·Filed 2017·Granted Apr 10, 2018·20 cites·20 claims
- 0393US11804828B2Dual duty cycle correction loop for a serializer/deserializer (SerDes) transmitter outputIBM·Filed 2022·Granted Oct 31, 2023·3 cites·20 claims
- 0492US10097383B1High speed DFEs with direct feedbackIBM·Filed 2017·Granted Oct 9, 2018·13 cites·24 claims
- 0591US10171281B24-level pulse amplitude modulation transmitter architectures utilizing quadrature clock phasesIBM·Filed 2017·Granted Jan 1, 2019·8 cites·20 claims
- 0690US8681839B2Calibration of multiple parallel data communications lines for high skew conditionsBULZACCHELLI JOHN F·Filed 2010·Granted Mar 25, 2014·16 cites·22 claims
- 0788US9674025B24-level pulse amplitude modulation transmitter architectures utilizing quadrature clock phasesIBM·Filed 2014·Granted Jun 6, 2017·9 cites·18 claims
- 0887US9942030B1Serial transmitter with feed forward equalizerIBM·Filed 2017·Granted Apr 10, 2018·6 cites·15 claims
- 0983US8085841B2Sampled current-integrating decision feedback equalizer and methodBULZACCHELLI JOHN F·Filed 2008·Granted Dec 27, 2011·11 cites·20 claims
- 1082US10284363B2Serial transmitter with feed forward equalizerIBM·Filed 2017·Granted May 7, 2019·3 cites·15 claims
- 1181US9876667B24-level pulse amplitude modulation transmitter architectures utilizing quadrature clock phasesIBM·Filed 2017·Granted Jan 23, 2018·3 cites·16 claims
- 1269US9684629B2Efficient calibration of a low power parallel data communications channelIBM·Filed 2016·Granted Jun 20, 2017·1 cites·15 claims
- 1362US8774228B2Timing recovery method and apparatus for an input/output bus with link redundancyBULZACCHELLI JOHN F·Filed 2011·Granted Jul 8, 2014·1 cites·23 claims
- 1461US9325542B2Power-scalable skew compensation in source-synchronous parallel interfacesGLOBALFOUNDRIES INC·Filed 2012·Granted Apr 26, 2016·1 cites·15 claims
- 1560US8842722B2Decision feedback equalizers with high-order continuous time feedbackDICKSON TIMOTHY O·Filed 2012·Granted Sep 23, 2014·2 cites·4 claims
- 1649US9001842B2Parallel receiver interface with receiver redundancyIBM·Filed 2013·Granted Apr 7, 2015·0 cites·21 claims
- 1748US9411750B2Efficient calibration of a low power parallel data communications channelDICKSON TIMOTHY O·Filed 2012·Granted Aug 9, 2016·0 cites·8 claims
- 1845US12015510B2Transmitter with uniform driver segment activityIBM·Filed 2022·Granted Jun 18, 2024·0 cites·20 claims
- 1944US8861513B2Fault tolerant parallel receiver interface with receiver redundancyIBM·Filed 2013·Granted Oct 14, 2014·0 cites·21 claims
- 2042US12088314B2Segmented digital-to-analog converter wireline driverIBM·Filed 2022·Granted Sep 10, 2024·0 cites·19 claims
- 2140US8824540B2Decision feedback equalizers with high-order continuous time feedbackDICKSON TIMOTHY O·Filed 2012·Granted Sep 2, 2014·0 cites·4 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →