Inventor · disambiguated record
Ting-Hsiang Hung
Also filed as: HUNG TING-HSIANG
1 granted patent·41 pending applications·2 citations·filing 2018–2025
19Inventor score
Top patents by PatentIndex Score
42 records- 0177US10361289B1Gate oxide formation through hybrid methods of thermal and deposition processes and method for producing the sameGLOBALFOUNDRIES INC·Filed 2018·Granted Jul 23, 2019·2 cites·18 claims
- 0270US2025323127A1Integrated circuit structure with deep via bar width tuningINTEL CORP·Filed 2025·Application pending·0 cites
- 0365US2025112120A1Integrated circuit structure with deep via bar width tuningINTEL CORP·Filed 2023·Application pending·0 cites
- 0460US2025311273A1Zero diffusion break for improving transistor densityINTEL CORP·Filed 2024·Application pending·0 cites
- 0558US2025308982A1Self-aligned patterned trench isolations for yield and performance improvementsINTEL CORP·Filed 2024·Application pending·0 cites
- 0658US2025386580A1Integrated circuit structures with backside isolation structureINTEL CORP·Filed 2024·Application pending·0 cites
- 0758US2025386578A1Contact over active gate structures with widened and lower capacitance insulating cap layers for advanced integrated circuit structure fabricationINTEL CORP·Filed 2024·Application pending·0 cites
- 0857US2025311272A1Gate-all-around devices with modulated number of active nanoribbonsINTEL CORP·Filed 2024·Application pending·0 cites
- 0957US2025311428A1Ribbon complementary fet (cfet) metal gate multi-voltage threshold integrationINTEL CORP·Filed 2024·Application pending·0 cites
- 1057US2025311427A1Deep via backside (dvb) partial recess for capacitance reduction in complementary fet (cfet) transistorsINTEL CORP·Filed 2024·Application pending·0 cites
- 1156US2025311353A1Dielectric wall used to separate gate dielectric between adjacent devicesINTEL CORP·Filed 2024·Application pending·0 cites
- 1256US2025311404A1Backside-patterned fin isolation structures between semiconductor devicesINTEL CORP·Filed 2024·Application pending·0 cites
- 1356US2025393250A1Integrated circuit structures having hybrid channel layoutINTEL CORP·Filed 2024·Application pending·0 cites
- 1455US2025311363A1Backside gate cut formationINTEL CORP·Filed 2024·Application pending·0 cites
- 1555US2025194211A1Conductive via with front-side and back-side connections with a source or drain regionINTEL CORP·Filed 2023·Application pending·0 cites
- 1655US2025142948A1Integrated circuit devices with self-aligned via-to-jumper connectionsINTEL CORP·Filed 2023·Application pending·0 cites
- 1754US2025212463A1Metal-all-around contact structure coupled with a source or drain regionINTEL CORP·Filed 2023·Application pending·0 cites
- 1854US2025204000A1Integrated circuit device with co-metalized electrical contactINTEL CORP·Filed 2023·Application pending·0 cites
- 1954US2025107212A1Airgap spacer between gate electrode and source or drain contactINTEL CORP·Filed 2023·Application pending·0 cites
- 2054US2025176255A1Back-side nanoribbon removalINTEL CORP·Filed 2023·Application pending·0 cites
- 2154US2025212470A1Integrated circuit device with backside isolaton regionINTEL CORP·Filed 2023·Application pending·0 cites
- 2254US2025204035A1Integrated circuit device with dielectric cut at n-p boundaryINTEL CORP·Filed 2023·Application pending·0 cites
- 2354US2025098260A1Integrated circuit structures with patch spacersINTEL CORP·Filed 2023·Application pending·0 cites
- 2454US2025113559A1Trench contact structure with etch-stop layerINTEL CORP·Filed 2023·Application pending·0 cites
- 2554US2025096114A1Via structure with improved substrate groundingINTEL CORP·Filed 2023·Application pending·0 cites
- 2654US2025089310A1Through-gate structure with an airgap spacer in a semiconductor deviceINTEL CORP·Filed 2023·Application pending·0 cites
- 2753US2025194179A1Integrated circuit structures with backside contacts and asymmetric source and drain regionsCHU TAO·Filed 2023·Application pending·0 cites
- 2853US2025113547A1Integrated circuit structures with internal spacers for 2d channel materialsINTEL CORP·Filed 2023·Application pending·0 cites
- 2953US2025169130A1Integrated circuit structures with different nanoribbon thicknessesINTEL CORP·Filed 2023·Application pending·0 cites
- 3053US2025087530A1Lateral etching process to remove metal gate foot structuresINTEL CORP·Filed 2023·Application pending·0 cites
- 3153US2025140649A1Integrated circuit devices with backside semiconductor structuresINTEL CORP·Filed 2023·Application pending·0 cites
- 3252US2025113595A1Multiple voltage threshold integrated circuit structure with local layout effect tuningINTEL CORP·Filed 2023·Application pending·0 cites
- 3352US2025107156A1Dielectric isolation between epitaxial regions and subfin regionsINTEL CORP·Filed 2023·Application pending·0 cites
- 3452US2025107175A1Integrated circuit structures having reduced local layout effectsINTEL CORP·Filed 2023·Application pending·0 cites
- 3551US2024222484A1Transistor with channel material in a stack with insulator material supportsINTEL CORP·Filed 2022·Application pending·0 cites
- 3651US2025194070A1Integrated circuit structures with transistor gate-channel arrangements for static random-access memoryCHU TAO·Filed 2023·Application pending·0 cites
- 3750US2025006734A1Performance optimization of transistors sharing channel structures of varying widthINTEL CORP·Filed 2023·Application pending·0 cites
- 3850US2025203975A1Integrated circuit device with semiconductor structure extending across gate in isolaton regionXU GUOWEI·Filed 2023·Application pending·0 cites
- 3948US2024088265A1Epitaxial regions extending between inner gate spacersINTEL CORP·Filed 2022·Application pending·0 cites
- 4047US2024105718A1Integrated circuit devices with protection liner between doped semiconductor regionsINTEL CORP·Filed 2022·Application pending·0 cites
- 4147US2024088217A1Barrier layer for dielectric recess mitigationINTEL CORP·Filed 2022·Application pending·0 cites
- 4246US2024105770A1Necked ribbon for better n workfunction filling and device performanceINTEL CORP·Filed 2022·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →