Inventor · disambiguated record
Todd Bystrom
Also filed as: BYSTROM TODD · BYSTROM TODD W
14 granted patents·3 pending applications·533 citations·filing 1998–2015
94Inventor score
Top patents by PatentIndex Score
17 records- 0198US7581121B2System for a memory device having a power down mode and methodRAMBUS INC·Filed 2005·Granted Aug 25, 2009·76 cites·21 claims
- 0298US6154821AMethod and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domainRAMBUS INC·Filed 1998·Granted Nov 28, 2000·237 cites·24 claims
- 0396US6842864B1Method and apparatus for configuring access times of memory devicesRAMBUS INC·Filed 2000·Granted Jan 11, 2005·99 cites·32 claims
- 0493US8756395B2Controlling DRAM at time DRAM ready to receive command when exiting power downBARTH RICHARD M·Filed 2012·Granted Jun 17, 2014·12 cites·22 claims
- 0590US7571330B2System and module including a memory device having a power down modeRAMBUS INC·Filed 2005·Granted Aug 4, 2009·14 cites·30 claims
- 0685US6879195B2PLL lock detection circuit using edge detectionRAMBUS INC·Filed 2003·Granted Apr 12, 2005·22 cites·22 claims
- 0781US7668271B2Clock-data recovery (“CDR”) circuit, apparatus and method for variable frequency dataRAMBUS INC·Filed 2003·Granted Feb 23, 2010·31 cites·27 claims
- 0880US8130891B2Clock-data recovery (“CDR”) circuit, apparatus and method for variable frequency dataKIM DENNIS·Filed 2010·Granted Mar 6, 2012·6 cites·22 claims
- 0980US7574616B2Memory device having a power down exit registerRAMBUS INC·Filed 2004·Granted Aug 11, 2009·14 cites·41 claims
- 1079US7084681B2PLL lock detection circuit using edge detection and a state machineRAMBUS INC·Filed 2005·Granted Aug 1, 2006·7 cites·16 claims
- 1176US9389637B2Methods and systems for recovering intermittent timing-reference signalsRAMBUS INC·Filed 2013·Granted Jul 12, 2016·4 cites·32 claims
- 1272US8127152B2Method of operation of a memory device and system including initialization at a first frequency and operation at a second frequency and a power down exit modeBARTH RICHARD M·Filed 2004·Granted Feb 28, 2012·10 cites·25 claims
- 1351US2005154817A1Method of operation and controlling a memory deviceFiled 2005·Application pending·0 cites
- 1451US2005154853A1Memory device and method of operation of a memory deviceFiled 2005·Application pending·0 cites
- 1549US9036436B2Supporting calibration for sub-rate operation in clocked memory systemsBANSAL AKASH·Filed 2012·Granted May 19, 2015·1 cites·20 claims
- 1643US9349422B2Supporting calibration for sub-rate operation in clocked memory systemsRAMBUS INC·Filed 2015·Granted May 24, 2016·0 cites·20 claims
- 1742US2005193183A1Method and apparatus for initializing dynamic random access memory (DRAM) devicesFiled 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →