Method of operation and controlling a memory device

Abstract

A method of operation of a memory device and system includes receiving a first and second value in embodiments. The first value is representative of a number of clock cycles of a clock signal that elapse between latching a column address and an access of data sensed from a row of memory cells in a memory array. A location of the data is based on the column address. The second value is representative of a number of clock cycles of the clock signal that elapse between the access of data from the memory array and outputting the data. The first and second values are received during an initialization sequence. Information in units of time that represents first and second timing parameters that pertains to the memory device is read from a storage location. The information that represents the first and second timing parameters are then converted from units of time to units of clock cycles to derive the first and second values.

1 - 24 . (canceled)  
   
   
       25 . A method of operation of a memory device having a memory array, the method comprising: 
 receiving a first value that is representative of a number of clock cycles of a clock signal to elapse between latching a column address and an access of data sensed from a row of memory cells in the memory array, wherein a location of the data is based on the column address; and    receiving a second value that is representative of a number of clock cycles of the clock signal to elapse between the access of data from the memory array and outputting the data.    
   
   
       26 . The method of  claim 25 , wherein receiving the first value occurs during an initialization sequence, and receiving the second value occurs during the initialization sequence.  
   
   
       27 . The method of  claim 25 , further including: 
 reading from a storage area, first information that represents a first timing parameter in units of time, wherein the first timing parameter pertains to the memory device; and    converting the first information that represents the first timing parameter from units of time to units of clock cycles of the clock signal to derive the first value.    
   
   
       28 . The method of  claim 27 , further including: 
 reading from the storage area, second information that represents a second timing parameter in units of time, wherein the second timing parameter pertains to the memory device; and    converting the information that represents the second timing parameter from units of time to units of clock cycles of the clock signal to derive the second value.    
   
   
       29 . The method of  claim 28 , wherein the storage area is included along with the memory device on a memory module.  
   
   
       30 . The method of  claim 29 , wherein the storage area is a serial presence detect device.  
   
   
       31 . A method of controlling a memory device having a memory array, the method comprising: 
 providing a first value to the memory device, wherein the first value is representative of a number of clock cycles to elapse between latching a column address and an access of data sensed from a row of memory cells in the memory array, wherein a location of the data is based on the column address; and    providing a second value to the memory device, wherein the second value is representative of a number of clock cycles to elapse between the access of data sensed from the row of memory cells and the memory device outputting the data.    
   
   
       32 . The method of  claim 31 , wherein providing the first value to the memory device occurs during an initialization sequence, and providing the second value to the memory device occurs during the initialization sequence.  
   
   
       33 . The method of  claim 31 , further including: 
 reading from a storage area, information that represents a first timing parameter in units of time, wherein the first timing parameter pertains to the memory device;    converting the information that represents the first timing parameter from units of time to units of clock cycles of a clock signal to derive the first value;    reading from the storage area, information that represents a second timing parameter in units of time, wherein the second timing parameter pertains to the memory device; and    converting the information that represents the second timing parameter from units of time to units of clock cycles of the clock signal to derive the second value.    
   
   
       34 . The method of  claim 33 , wherein the storage area is included along with the memory device on a memory module.  
   
   
       35 . The method of  claim 34 , wherein the storage area is a serial presence detect device.  
   
   
       36 . The method of  claim 33 , wherein converting the information that represents the first timing parameter includes dividing a time period pertaining to the timing parameter by a period of the clock signal.  
   
   
       37 . The method of  claim 36 , wherein converting the information further includes rounding to a next whole number of clock cycles when a fractional number of clock cycles results when dividing the time period by the period of the clock signal.  
   
   
       38 . The method of  claim 31 , further including: 
 reading from a storage area, information that represents a time to sense a row of the memory device;    converting the information to units of clock cycles of the clock signal to derive a value that represents the time to sense the row of memory cells; and    storing the value that represents the time to sense the row of memory cells in a memory controller.    
   
   
       39 . The method of  claim 31 , further including: 
 reading from a storage area, information that represents a time between a row access operation of the memory device and column access operation of the memory device;    converting the information to units of clock cycles of the clock signal to derive a value that represents the time between the row access operation of the memory device and column access operation of the memory device; and    storing the value that represents the time between the row access operation of the memory device and column access operation of the memory device in a memory controller.    
   
   
       40 . The method of  claim 31 , further including: 
 reading from a storage area, information that represents a time between a row access operation of the memory device and a precharge operation of the memory device;    converting the information to units of clock cycles of the clock signal to derive a value that represents the time between the row access operation of the memory device and the precharge operation of the memory device; and    storing the value that represents a time between the row access operation of the memory device and the precharge operation of the memory device in a memory controller.    
   
   
       41 . The method of  claim 31 , further including: 
 reading from a storage area, information that represents a time between a row sense operation applied to a first bank of the memory device and a row sense operation applied to a second bank of the memory device;    converting the information to units of clock cycles of the clock signal to derive a value that represents the time between the row sense operation applied to the first bank of the memory device and the row sense operation applied to the second bank of the memory device; and    storing the value that represents the time between the row sense operation applied to the first bank of the memory device and the row sense operation applied to the second bank of the memory device in a memory controller.    
   
   
       42 . The method of  claim 31 , further including: 
 reading from a storage area, information that represents a time between a precharge operation applied to a first bank of the memory device and a precharge operation applied to a second bank of the memory device;    converting the information to units of clock cycles of the clock signal to derive a value that represents the time between the precharge operation applied to the first bank of the memory device and the precharge operation applied to the second bank of the memory device; and    storing the value that represents the precharge operation applied to the first bank of the memory device and the precharge operation applied to the second bank of the memory device in a memory controller.    
   
   
       43 . A method of operation in a system: 
 reading from a storage location in the system, information representing a plurality of timing parameters pertaining to a memory device having a memory array, wherein the information includes information representing a first timing parameter and information representing a second timing parameter;    determining from the information representing the first timing parameter, a first value that is representative of a number of clock cycles to elapse between latching a column address and an access of data sensed from a row of memory cells in the memory array, wherein a location of the data is based on the column address; and    determining from the information representing the second timing parameter, a second value that is representative of a number of clock cycles to elapse between the access of data from the memory array and outputting the data.    
   
   
       44 . The method of  claim 43 , wherein reading the information representing the plurality of timing parameters occurs during an initialization sequence of the system.  
   
   
       45 . The method of  claim 43 , wherein determining the first value includes converting the information representing the first timing parameter from units of time to units of clock cycles of the clock signal.  
   
   
       46 . The method of  claim 43 , wherein determining the second value includes converting the information representing the second timing parameter from units of time to units of clock cycles of the clock signal.  
   
   
       47 . The method of  claim 46 , wherein the storage location is a device included along with the memory device on a memory module.  
   
   
       48 . The method of  claim 47 , wherein the storage location is a serial presence detect device.  
   
   
       49 . The method of  claim 45 , wherein converting the information representing the first timing parameter further includes dividing a time period of the first timing parameter by a period of the clock signal.  
   
   
       50 . The method of  claim 49 , wherein converting the first timing parameter further includes rounding to a next whole number of clock cycles of the clock signal when a fractional number of clock cycles results when dividing the time period of the first timing parameter by the period of the clock signal.  
   
   
       51 . The method of  claim 49 , further including reading from the storage location in the system, information representing the period of the clock signal.  
   
   
       52 . The method of  claim 43 , wherein the information includes information that represents a time to sense a row of the memory device.  
   
   
       53 . The method of  claim 43 , wherein the information includes information that represents a time between a row access operation of the memory device and column access operation of the memory device.  
   
   
       54 . The method of  claim 43 , wherein the information includes information that represents a time between a row access operation of the memory device and a precharge operation of the memory device.  
   
   
       55 . The method of  claim 43 , wherein the information includes information that represents a time between a row sense operation applied to a first bank of the memory device and a row sense operation applied to a second bank of the memory device.  
   
   
       56 . The method of  claim 43 , wherein the information includes information that represents a time between a precharge operation applied to a first bank of the memory device and a precharge operation applied to a second bank of the memory device.  
   
   
       57 . A method of operation of a memory device having a memory array, the method comprising: 
 step for receiving a first value that is representative of a number of clock cycles of a clock signal to elapse after receiving a column address before an access of data held in a plurality of sense amplifiers, the data being sensed by the plurality of sense amplifiers from a row of memory cells in the memory array, wherein a location of the data accessed is based on the column address; and    step for receiving a second value that is representative of a number of clock cycles of the clock signal to elapse between the access of data from the memory array and outputting the data.