Inventor · disambiguated record
Toshinori Hosokawa
Also filed as: HOSOKAWA TOSHINORI
15 granted patents·2 pending applications·166 citations·filing 1990–2002
93Inventor score
Technology areasG01R
Top patents by PatentIndex Score
17 records- 0171US6449743B1Method of generating test sequencesMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 1999·Granted Sep 10, 2002·32 cites·8 claims
- 0262US6292915B1Method of design for testability and method of test sequence generationMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 1998·Granted Sep 18, 2001·24 cites·14 claims
- 0357US5305328AMethod of test sequence generationMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 1990·Granted Apr 19, 1994·19 cites·9 claims
- 0455US5748646ADesign-for-testability method for path delay faults and test pattern generation method for path delay faultsMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 1996·Granted May 5, 1998·18 cites·13 claims
- 0554US6651206B2Method of design for testability, test sequence generation method and semiconductor integrated circuitMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2001·Granted Nov 18, 2003·5 cites·5 claims
- 0653US6708315B2Method of design for testability, method of design for integrated circuits and integrated circuitsMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2001·Granted Mar 16, 2004·6 cites·22 claims
- 0749US6185721B1Method of design for testability at RTL and integrated circuit designed by the sameMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 1997·Granted Feb 6, 2001·14 cites·23 claims
- 0844US6016564AMethod of design for testability, method of design for avoiding bus error and integrated circuitMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 1997·Granted Jan 18, 2000·11 cites·18 claims
- 0943US6510535B1Method of design for testability for integrated circuitsMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 1999·Granted Jan 21, 2003·11 cites·14 claims
- 1042US6271677B1Semiconductor integrated circuit and method for testing the semiconductor integrated circuitMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2000·Granted Aug 7, 2001·2 cites·27 claims
- 1139US5319647AMethod and apparatus for performing automatic test pattern generationMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 1990·Granted Jun 7, 1994·8 cites·26 claims
- 1238US5737341AMethod of generating test sequence and apparatus for generating test sequenceMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 1996·Granted Apr 7, 1998·7 cites·9 claims
- 1335US7437340B2Designing of a logic circuit for testabilitySEMICONDUCTOR TECH ACAD RES CT·Filed 2002·Granted Oct 14, 2008·0 cites·12 claims
- 1435US5483543ATest sequence generation methodMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 1992·Granted Jan 9, 1996·5 cites·11 claims
- 1534US6253343B1Method of design for testability test sequence generation method and semiconductor integrated circuitMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 1998·Granted Jun 26, 2001·4 cites·16 claims
- 1634US2003188239A1Compacted test plan generation for integrated circuit testing, test sequence generation, and testFiled 2002·Application pending·0 cites
- 1732US2003009716A1Method of design for testability for integrated circuitsFiled 2002·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →