Method of design for testability and method of test sequence generation

Abstract

The invention provides a method of design for testability at RTL which can guarantee high fault coverage and a method of test sequence generation for easily generating test sequences for an RTL circuit which is designed to be easily testable by the method of design for testability. In the RTL circuit, scannable registers are selected so that the RTL circuit can attain an easily testable circuit structure such as an acyclic structure. This RTL circuit is timeframe expanded on the basis of a predetermined evaluation function and logically synthesized, so as to generate a timeframe expanded combinational circuit, that is, a gate level timeframe expanded circuit, as a circuit for test sequence generation. For the timeframe expanded combinational circuit, test patterns for multiple stuck-at faults are generated, the test patterns are transformed into test sequences on the basis of data on timeframes including primary inputs and pseudo-primary inputs, and the test sequences are transformed into scanning test sequences in view of a scan shift operation.

What is claimed is:  
     
       1. A method of design for testability for modifying design of an RTL circuit, that is, an integrated circuit designed at register transfer level, so as to attain testability after manufacture, comprising: 
       a first step of specifying as an easily testable circuit structure, an n-fold line-up structure in which paths between an arbitrary pair of a register of the circuit and a primary output or a pseudo-primary output have n or less sorts of sequential depths, where n is a natural number, and specifying a value of n; and  
       a second step of selecting scannable registers among registers included in said RTL circuit so that said RTL circuit in test has said easily testable circuit structure specified in said first step in assuming a normal data input of a scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input.  
     
     
       2. A method of design for testability for modifying design of an RTL circuit, that is, an integrated circuit designed at register transfer level, so as to attain testability after manufacture, comprising: 
       a first step of specifying as an easily testable circuit structure, an n-fold acyclic structure in which paths from a primary or pseudo-primary input to a primary or pseudo-primary output contain n or less types of register sets, each said type of register set includes a different number of registers, where n is a natural number, and specifying a value of n; and  
       a second step of selecting scannable registers among registers included in said RTL circuit so that said RTL circuit in test has said easily testable circuit structure specified in said first step in assuming a normal data input of a scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input.  
     
     
       3. A method of design for testability for modifying design of an RTL circuit, that is, an integrated circuit designed at register transfer level, so as to attain testability after manufacture, comprising: 
       a first step of specifying as an easily testable circuit structure, a structure in which each of paths from primary or pseudo-primary inputs to primary or pseudo-primary outputs contains n or less stages of gates, where n is 0 or a natural number, and specifying a value of n; and  
       a second step of selecting scannable registers among registers included in said RTL circuit so that said RTL circuit in test has said easily testable circuit structure specified in said first step in assuming a normal data input of a scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input.  
     
     
       4. A method of design for testability for modifying design of an RTL circuit, that is, an integrated circuit designed at register transfer level, so as to attain testability after manufacture, comprising: 
       a first step of specifying an easily testable circuit structure; and  
       a second step of selecting scannable registers among registers included in said RTL circuit so that said RTL circuit in test has said easily testable circuit structure specified in said first step in assuming a normal data input of a scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input,  
       wherein said second step includes:  
       a first process for partitioning said RTL circuit into plural blocks;  
       a second process for selecting, in each of said blocks, registers reachable in a direction from an output to an input of said block by passing merely through combinational facilities as said scannable registers; and  
       a third process for selecting said scannable registers among said registers of said RTL circuit so that each block in test attains said easily testable circuit structure in assuming a normal data input of a scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input.  
     
     
       5. A method of test sequence generation for an RTL circuit, that is, an integrated circuit designed at register transfer level, said RTL circuit having an acyclic structure in test or having a structure in which scannable registers are selected and an acyclic structure is attained in test in assuming a normal data input of a scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input, comprising: 
       a first step of converting said RTL circuit into a timeframe expanded combinational circuit, that is, a gate level timeframe expanded circuit;  
       a second step of generating test patterns for said timeframe expanded combinational circuit generated in said first step; and  
       a third step of transforming said test patterns generated in said second step into test sequences for the sequential circuit on the basis of data on timeframes including each of primary inputs and pseudo-primary inputs of said timeframe expanded combinational circuit generated in said first step,  
       wherein said first step includes:  
       an RTL timeframe expanding process for timeframe expanding said RTL circuit on the basis of a predetermined evaluation function;  
       a logic synthesizing process for converting said RTL circuit into a gate level circuit through logic synthesis; and  
       a test sequence generation circuit generating process for generating said timeframe expanded combinational circuit on the basis of the timeframe expanded RTL circuit obtained in said RTL timeframe expanding process and the gate level circuit generating in said logic synthesizing process.  
     
     
       6. The method of test sequence generation of claim  5 , 
       wherein, in said RTL timeframe expanding process, said RTL circuit is timeframe expanded by using a total number of combinational facilities included in each timeframe or the total of the numbers of gates estimated for the combinational facilities in each timeframe as said predetermined evaluation function, with minimizing said predetermined evaluation function.  
     
     
       7. The method of test sequence generation of claim  5 , 
       wherein, in said RTL timeframe expanding process, said RTL circuit is timeframe expanded by using a number of timeframes including a pseudo-primary input or a pseudo-primary output as said predetermined evaluation function, with minimizing said predetermined evaluation function.  
     
     
       8. The method of test sequence generation of claim  5 , 
       wherein, in said RTL timeframe expanding process, said RTL circuit is timeframe expanded by using, as said predetermined evaluation function, a value obtained by subtracting a number of registers each of which the pseudo-primary input corresponding thereto is included in a timeframe following a timeframe including its corresponding pseudo-primary output from a sum of a total number of timeframes including each pseudo-primary input and a total number of timeframes including each pseudo-primary output, with minimizing said predetermined evaluation function.  
     
     
       9. The method of test sequence generation of claim  5 , 
       wherein, in said RTL timeframe expanding process, said RTL circuit is timeframe expanded by using a total number of primary inputs included in each timeframe as said predetermined evaluation function, with maximizing said predetermined evaluation function.  
     
     
       10. The method of test sequence generation of claim  5 , 
       wherein said RTL timeframe expanding process includes:  
       a first process for obtaining a maximum sequential depth of each of primary outputs and pseudo-primary outputs of said RTL circuit;  
       a second process for sorting said primary outputs and pseudo-primary outputs of said RTL circuit in a descending order of said maximum sequential depths thereof obtained in said first process;  
       a third process for setting a value obtained by adding one to the maximum value of said maximum sequential depth obtained in said first process as a number of timeframes in timeframe expansion; and  
       a fourth process for conducting timeframe expansion with respect to said primary outputs and pseudo-primary outputs in accordance with said predetermined evaluation function in the sorted order obtained in said second process.  
     
     
       11. The method of test sequence generation of claim  5 , 
       wherein said first step includes a pre-process for grouping, in said RTL circuit, combinational facilities containing none of registers, primary inputs and primary outputs in a path therebetween,  
       in said RTL timeframe expanding process, the timeframe expansion is conducted with said combinational facilities grouped in said pre-process regarded as one combinational facility, and  
       in said logic synthesizing process, the logic synthesis is conducted by using said combinational facilities grouped in said pre-process as one unit.  
     
     
       12. A method of test sequence generation for an RTL circuit, that is, an integrated circuit designed at register transfer level, said RTL circuit having an acyclic structure in test or having a structure in which scannable registers are selected and an acyclic structure is attained in test in assuming a normal data input of a scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input, comprising: 
       a first step of converting said RTL circuit into a timeframe expanded combinational circuit, that is, a gate level timeframe expanded circuit;  
       a second step of generating test patterns for said timeframe expanded combinational circuit generated in said first step; and  
       a third step of transforming said test patterns generated in said second step into test sequences for the sequential circuit on the basis of data on timeframes including each of primary inputs and pseudo-primary inputs of said timeframe expanded combinational circuit generated in said first step,  
       wherein said first step includes:  
       a logic synthesizing process for logically synthesizing said RTL circuit; and  
       a gate level timeframe expanding process for generating said timeframe expanded combinational circuit through timeframe expansion of said gate level circuit generated in said logic synthesizing process on the basis of a predetermined evaluation function.  
     
     
       13. The method of test sequence generation of claim  12 , wherein, in said gate level timeframe expanding process, said gate level circuit is timeframe expanded by using a total number of gates included in each timeframe as said predetermined evaluation function, with minimizing said predetermined evaluation function. 
     
     
       14. A method of test sequence generation for an RTL circuit, that is, an integrated circuit designed at register transfer level, said RTL circuit having an acyclic structure in test or having a structure in which scannable registers are selected and an acyclic structure is attained in test in assuming a normal data input of a scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input, comprising: 
       a first step of converting said RTL circuit into a timeframe expanded combinational circuit, that is, a gate level timeframe expanded circuit;  
       a second step of generating test patterns for said timeframe expanded combinational circuit generated in said first step; and  
       a third step of transforming said test patterns generated in said second step into test sequences for the sequential circuit on the basis of data on timeframes including each of primary inputs and pseudo-primary inputs of said timeframe expanded combinational circuit generated in said first step,  
       wherein, in said third step, said test patterns are transformed into said test sequences with one scan path formed by using scan FFs composing a register corresponding to a pseudo-primary output included in one timeframe and scan FFs composing a register corresponding to a pseudo-primary input included in another following timeframe.