Inventor · disambiguated record
Tse-Yu Yeh
Also filed as: YEH TSE-YU
42 granted patents·3 pending applications·1,814 citations·filing 1995–2012
99Inventor score
Top patents by PatentIndex Score
45 records- 0191US8352685B2Combining write buffer with dynamically adjustable flush metricsAPPLE INC·Filed 2010·Granted Jan 8, 2013·16 cites·13 claims
- 0290US6185676B1Method and apparatus for performing early branch prediction in a microprocessorINTEL CORP·Filed 1997·Granted Feb 6, 2001·190 cites·33 claims
- 0390US5802602AMethod and apparatus for performing reads of related data from a set-associative cache memoryINTEL CORP·Filed 1997·Granted Sep 1, 1998·182 cites·22 claims
- 0489US7752474B2L1 cache flush when processor is entering low power modeAPPLE INC·Filed 2006·Granted Jul 6, 2010·18 cites·23 claims
- 0589US5903750ADynamic branch prediction for branch instructions with multiple targetsINST THE DEV OF EMERGING ARCHI·Filed 1996·Granted May 11, 1999·161 cites·19 claims
- 0687US8171326B2L1 flush mechanism to flush cache for power down and handle coherence during flush and/or after power downKELLER JAMES B·Filed 2010·Granted May 1, 2012·8 cites·20 claims
- 0784US7203817B2Power consumption reduction in a pipeline by stalling instruction issue on a load missBROADCOM CORP·Filed 2002·Granted Apr 10, 2007·39 cites·13 claims
- 0883US5742804AInstruction prefetch mechanism utilizing a branch predict instructionINST THE DEV OF EMERGING ARCHI·Filed 1996·Granted Apr 21, 1998·109 cites·12 claims
- 0982US6427206B1Optimized branch predictions for strongly predicted compiler branchesINTEL CORP·Filed 1999·Granted Jul 30, 2002·111 cites·28 claims
- 1080US7721066B2Efficient encoding for detecting load dependency on store with misalignmentAPPLE INC·Filed 2007·Granted May 18, 2010·9 cites·17 claims
- 1180US6240510B1System for processing a cluster of instructions where the instructions are issued to the execution units having a priority order according to a template associated with the cluster of instructionsINTEL CORP·Filed 1998·Granted May 29, 2001·89 cites·32 claims
- 1279US7996646B2Efficient encoding for detecting load dependency on store with misalignmentAPPLE INC·Filed 2010·Granted Aug 9, 2011·5 cites·16 claims
- 1375US6304960B1Validating prediction for branches in a cluster via comparison of predicted and condition selected tentative target addresses and validation of branch conditionsINTEL CORP·Filed 1998·Granted Oct 16, 2001·70 cites·25 claims
- 1474US7647518B2Replay reduction for power savingAPPLE INC·Filed 2006·Granted Jan 12, 2010·6 cites·19 claims
- 1572US8117404B2Misalignment predictorYEH TSE-YU·Filed 2005·Granted Feb 14, 2012·6 cites·31 claims
- 1672US6430674B1Processor executing plural instruction sets (ISA's) with ability to have plural ISA's in different pipeline stages at same timeINTEL CORP·Filed 1998·Granted Aug 6, 2002·71 cites·50 claims
- 1772US6212603B1Processor with apparatus for tracking prefetch and demand fetch instructions serviced by cache memoryINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted Apr 3, 2001·77 cites·28 claims
- 1871US6611910B2Method for processing branch operationsIDEA CORP·Filed 1998·Granted Aug 26, 2003·49 cites·15 claims
- 1971US6542981B1Microcode upgrade and special function support by executing RISC instruction to invoke resident microcodeINTEL CORP·Filed 1999·Granted Apr 1, 2003·57 cites·24 claims
- 2071US5805878AMethod and apparatus for generating branch predictions for multiple branch instructions indexed by a single instruction pointerINTEL CORP·Filed 1997·Granted Sep 8, 1998·64 cites·33 claims
- 2170US6553488B2Method and apparatus for branch prediction using first and second level branch prediction tablesINTEL CORP·Filed 1998·Granted Apr 22, 2003·53 cites·25 claims
- 2268US6976152B2Comparing operands of instructions against a replay scoreboard to detect an instruction replay and copying a replay scoreboard to an issue scoreboardBROADCOM CORP·Filed 2002·Granted Dec 13, 2005·14 cites·31 claims
- 2368US6092188AProcessor and instruction set with predict instructionsINTEL CORP·Filed 1999·Granted Jul 18, 2000·55 cites·3 claims
- 2466US6877085B2Mechanism for processing speclative LL and SC instructions in a pipelined processorBROADCOM CORP·Filed 2002·Granted Apr 5, 2005·10 cites·19 claims
- 2565US6012134AHigh-performance processor with streaming buffer that facilitates prefetching of instructionsINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted Jan 4, 2000·55 cites·16 claims
- 2664US8566528B2Combining write buffer with dynamically adjustable flush metricsAPPLE INC·Filed 2012·Granted Oct 22, 2013·1 cites·17 claims
- 2764US7269714B2Inhibiting of a co-issuing instruction in a processor having different pipeline lengthsBROADCOM CORP·Filed 2002·Granted Sep 11, 2007·10 cites·6 claims
- 2863US7162613B2Mechanism for processing speculative LL and SC instructions in a pipelined processorBROADCOM CORP·Filed 2005·Granted Jan 9, 2007·2 cites·5 claims
- 2963US6237077B1Instruction template for efficient processing clustered branch instructionsIDEA CORP·Filed 1997·Granted May 22, 2001·42 cites·7 claims
- 3062US6282636B1Decentralized exception processing systemINTEL CORP·Filed 1998·Granted Aug 28, 2001·37 cites·20 claims
- 3161US8171240B1Misalignment predictorYEH TSE-YU·Filed 2012·Granted May 1, 2012·1 cites·20 claims
- 3258US8255670B2Replay reduction for power savingCHANG PO-YUNG·Filed 2009·Granted Aug 28, 2012·2 cites·11 claims
- 3358US6253315B1Return address predictor that uses branch instructions to track a last valid return addressINTEL CORP·Filed 1998·Granted Jun 26, 2001·33 cites·14 claims
- 3454US5815700ABranch prediction table having pointers identifying other branches within common instruction cache linesINTEL CORP·Filed 1995·Granted Sep 29, 1998·29 cites·18 claims
- 3552US7100064B2Limiting performance in an integrated circuit to meet export restrictionsBROADCOM CORP·Filed 2002·Granted Aug 29, 2006·3 cites·11 claims
- 3652US6353805B1Apparatus and method for cycle accounting in microprocessorsINTEL CORP·Filed 1998·Granted Mar 5, 2002·25 cites·52 claims
- 3751US6438682B1Method and apparatus for predicting loop exit branchesINTEL CORP·Filed 1998·Granted Aug 20, 2002·23 cites·23 claims
- 3849US6629238B1Predicate controlled software pipelined loop processing with prediction of predicate writing and value prediction for use in subsequent iterationINTEL CORP·Filed 1999·Granted Sep 30, 2003·21 cites·25 claims
- 3949US6052802AApparatus and method for cycle accounting in microprocessorsINTEL CORP·Filed 1997·Granted Apr 18, 2000·22 cites·47 claims
- 4046US2005066153A1Method for processing branch operationsFiled 2003·Application pending·0 cites
- 4145US2008086594A1Uncacheable load mergingPA SEMI INC·Filed 2006·Application pending·0 cites
- 4243US6871275B1Microprocessor having a branch predictor using speculative branch registersINTEL CORP·Filed 1996·Granted Mar 22, 2005·16 cites·9 claims
- 4343US2005149698A1Scoreboarding mechanism in a pipeline that includes replays and redirectsFiled 2005·Application pending·0 cites
- 4440US5987599ATarget instructions prefetch cacheINTEL CORP·Filed 1997·Granted Nov 16, 1999·12 cites·23 claims
- 4535US6044456AElectronic system and method for maintaining synchronization of multiple front-end pipelinesINTEL CORP·Filed 1998·Granted Mar 28, 2000·11 cites·25 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →