Inventor · disambiguated record
Tze-Hsiang Chao
Also filed as: CHAO TZE · CHAO TZE-HSIANG
13 granted patents·3 pending applications·141 citations·filing 1983–2024
91Inventor score
Top patents by PatentIndex Score
16 records- 0180US5085837AMethod for purifying TiO2 ore by alternate leaching with an aqueous solution of an alkali metal compound and an aqueous solution of mineral acidDU PONT·Filed 1990·Granted Feb 4, 1992·23 cites·26 claims
- 0280US5011666AMethod for purifying TiO2 oreDU PONT·Filed 1988·Granted Apr 30, 1991·28 cites·26 claims
- 0377US5181956AMethod for purifying TiO2 oreDU PONT·Filed 1991·Granted Jan 26, 1993·21 cites·20 claims
- 0474US5490976AContinuous ore reaction process by fluidizingDU PONT·Filed 1994·Granted Feb 13, 1996·23 cites·17 claims
- 0574US2025119121A1Impedance calibration circuit and methodM31 TECH CORP·Filed 2024·Application pending·0 cites
- 0672US7034589B2Multi-stage delay clock generatorSILICON INTEGRATED SYS CORP·Filed 2004·Granted Apr 25, 2006·20 cites·18 claims
- 0768US12244282B2Impedance calibration circuit and methodM31 TECH CORP·Filed 2023·Granted Mar 4, 2025·0 cites·20 claims
- 0862US7183821B1Apparatus and method of controlling clock phase alignment with dual loop of hybrid phase and time domain for clock source synchronizationSILICON INTEGRATED SYS CORP·Filed 2005·Granted Feb 27, 2007·4 cites·31 claims
- 0956US7202716B1Apparatus and method of controlling and tuning a fine calibration for clock source synchronization in dual loop of hybrid phase and time domainSILICON INTEGRATED SYS CORP·Filed 2005·Granted Apr 10, 2007·3 cites·34 claims
- 1055US7208403B2Tile-based routing method of a multi-layer circuit board and related structureSILICON INTEGRATED SYS CORP·Filed 2006·Granted Apr 24, 2007·2 cites·16 claims
- 1144US7411429B2System and method for clock switchingSILICON INTEGRATED SYS CORP·Filed 2005·Granted Aug 12, 2008·0 cites·23 claims
- 1244US4532113AIron chloride waste treatment in molten saltDU PONT·Filed 1983·Granted Jul 30, 1985·8 cites·7 claims
- 1341US2007241456A1Conductive structure for electronic deviceSILICON INTEGRATED SYS CORP·Filed 2006·Application pending·0 cites
- 1440US7043828B2Tile-based routing method of a multi-layer circuit boardSILICON INTEGRATED SYS CORP·Filed 2003·Granted May 16, 2006·2 cites·8 claims
- 1540US4655839ALandfillable composition from iron chloride waste treatment in molten saltDU PONT·Filed 1985·Granted Apr 7, 1987·7 cites·2 claims
- 1640US2004057548A1Quasi-synchronous multi-stage event synchronization apparatusSILICON INTEGRATED SYSTEM CORP·Filed 2002·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →