Quasi-synchronous multi-stage event synchronization apparatus

Abstract

The present invention relates to a quasi-synchronous multi-stage event synchronization apparatus by a phase lock loop (PLL) control circuit and a quasi-synchronous multi-stage synchronizer to tolerate clock uncertainty and speed up the synchronizing process between the asynchronous digital circuits from producing-end to consuming-end in the computer system. The phase lock loop (PLL) control circuit generates a pair of well-controlled clocks, PDU_CLK, CSM_CLK, assigned to producing-end and consuming-end and a pair of clock phase indicating signals, PDU_SYNC_PULSE, CSM_SYNC_PULSE, associated with the pair of well-controlled clocks. The quasi-synchronous multi-stage synchronizer routes the series of sync events into a synchronization stage with minimal synchronization delay from producing-end to consuming-end.

What is claimed is:  
     
         1 . A quasi-synchronous multi-stage event synchronization apparatus for synchronizing a series of sync events from a producing-end to a consuming-end, the clocks of said producing-end and said consuming-end operating at different phases, comprising: 
 a phase lock loop (PLL) control circuit for generating a pair of well-controlled clocks assigned to said producing-end and said consuming-end and a pair of clock phase indicating signals associated with said pair of well-controlled clocks; and    a quasi-synchronous multi-stage synchronizer for routing said series of sync events into a synchronization stage with minimal synchronization delay from said producing-end to said consuming-end.    
     
     
         2 . The apparatus according to  claim 1 , wherein said the clocks of said producing-end and said consuming-end operate at different frequencies.  
     
     
         3 . The apparatus according to  claim 1 , wherein said the clocks of said producing-end and said consuming-end operate at the same frequency.  
     
     
         4 . The apparatus according to  claim 1 , wherein said phase lock loop (PLL) control circuit further comprises: 
 a pair of phase lock loop components for locking the clock phases, making the clocks of said producing-end and said consuming-end to be kept at in-phase relationship, and providing said pair of clock phase indicating signals;    a group of I/O buffers for providing a input path to convert a external clock source into a internal silicon chip and two clock feedback paths for the clocks at said producing-end and said consuming-end; and    a latch component for keeping a predetermined value of clock frequency ratio after said pair of phase lock loop components are reset.    
     
     
         5 . The apparatus according to  claim 1 , wherein said quasi-synchronous multi-stage synchronizer further comprises: 
 a synchronization unit for synchronizing said series of routed sync events by said synchronization stage from said producing-end to said consuming-end;    a routing unit for deciding and routing said series sync event into said synchronization stage in said synchronization unit; and    an in-phase mask generator for generating a synchronized event mask signal at a in-phase sync phase.    
     
     
         6 . The apparatus according to  claim 5 , wherein said synchronization unit further comprises: 
 a general clocked synchronizer stage group for converting a plurality of routed sync events into a plurality of synced events that can be safely sampled by the clock of said consuming-end;    a general pass-through synchronizer stage group for converting a plurality of routed sync events into a plurality of synced events that can be safely sampled by the clock of said consuming-end; and    an in-phase pass-through synchronizer stage group for converting a plurality of routed sync event into a plurality of synced events that can be safely sampled by the clock of said consuming-end.    
     
     
         7 . The apparatus according to  claim 5 , wherein said routing unit further comprises: 
 a sync phase generator for generating a sync phase indicator signal of said producing-end; and    a sync stage switcher for routing said series of sync events, and dispatching said sync events into said synchronization stage in said synchronization unit.